Alexandre Ghiti 0ddd7eaffa riscv: Fix BUILTIN_DTB for sifive and microchip soc ... Fix BUILTIN_DTB config which resulted in a dtb that was actually not built into the Linux image: in the same manner as Canaan soc does, create an object file from the dtb file that will get linked into the Linux image. Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-06-11 21:07:09 -07:00
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boot	riscv: Fix BUILTIN_DTB for sifive and microchip soc	2021-06-11 21:07:09 -07:00
configs	RISC-V: Enable Microchip PolarFire ICICLE SoC	2021-04-26 08:31:32 -07:00
errata	riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled	2021-06-01 21:16:41 -07:00
include	riscv: alternative: fix typo in macro name	2021-06-10 20:35:05 -07:00
kernel	riscv: xip: support runtime trap patching	2021-06-10 16:16:06 -07:00
lib	riscv: Add support for function error injection	2021-01-14 15:09:09 -08:00
mm	riscv: mm: Fix W+X mappings at boot	2021-06-01 21:15:09 -07:00
net	riscv: bpf: Avoid breaking W^X	2021-04-26 08:25:14 -07:00
Kbuild	riscv: Allow device trees to be built into the kernel	2020-05-18 11:38:05 -07:00
Kconfig	riscv: code patching only works on !XIP_KERNEL	2021-06-10 16:33:50 -07:00
Kconfig.debug
Kconfig.erratas	riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y	2021-05-06 09:40:13 -07:00
Kconfig.socs	RISC-V Patches for the 5.13 Merge Window, Part 1	2021-05-06 09:24:18 -07:00
Makefile	riscv: Use -mno-relax when using lld linker	2021-05-29 11:40:16 -07:00