c11e3b48db
Probe the UARTs on SEAD3 boards using device tree rather than platform code, in order to reduce the amount of the latter. This requires that CONFIG_SERIAL_OF_PLATFORM be enabled, so enable it in sead3_defconfig. The SEAD3 DT shim code is extended to read bootloader environment variables to determine the appropriate UART & mode for kernel console output & set the stdout-path property of the chosen node accordingly. In contrast to the old platform code, which appears to have only ever set "console=ttyS0,38400n8r" with the code in console_config never having an effect, this will honor the "yamontty" environment variable to select between the 2 UARTs on the board and then check the "modetty0" or "modetty1" variable as appropriate to determine the UART configuration. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14048/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/bootinfo.h>
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#include <asm/cacheflush.h>
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#include <asm/traps.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/fw/fw.h>
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extern char except_vec_nmi;
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extern char except_vec_ejtag_debug;
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static void __init mips_nmi_setup(void)
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{
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void *base;
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base = cpu_has_veic ?
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(void *)(CAC_BASE + 0xa80) :
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(void *)(CAC_BASE + 0x380);
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#ifdef CONFIG_CPU_MICROMIPS
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/*
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* Decrement the exception vector address by one for microMIPS.
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*/
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memcpy(base, (&except_vec_nmi - 1), 0x80);
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/*
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* This is a hack. We do not know if the boot loader was built with
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* microMIPS instructions or not. If it was not, the NMI exception
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* code at 0x80000a80 will be taken in MIPS32 mode. The hand coded
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* assembly below forces us into microMIPS mode if we are a pure
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* microMIPS kernel. The assembly instructions are:
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*
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* 3C1A8000 lui k0,0x8000
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* 375A0381 ori k0,k0,0x381
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* 03400008 jr k0
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* 00000000 nop
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*
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* The mode switch occurs by jumping to the unaligned exception
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* vector address at 0x80000381 which would have been 0x80000380
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* in MIPS32 mode. The jump to the unaligned address transitions
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* us into microMIPS mode.
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*/
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if (!cpu_has_veic) {
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void *base2 = (void *)(CAC_BASE + 0xa80);
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*((unsigned int *)base2) = 0x3c1a8000;
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*((unsigned int *)base2 + 1) = 0x375a0381;
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*((unsigned int *)base2 + 2) = 0x03400008;
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*((unsigned int *)base2 + 3) = 0x00000000;
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flush_icache_range((unsigned long)base2,
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(unsigned long)base2 + 0x10);
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}
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#else
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memcpy(base, &except_vec_nmi, 0x80);
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#endif
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flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
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}
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static void __init mips_ejtag_setup(void)
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{
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void *base;
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base = cpu_has_veic ?
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(void *)(CAC_BASE + 0xa00) :
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(void *)(CAC_BASE + 0x300);
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#ifdef CONFIG_CPU_MICROMIPS
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/* Deja vu... */
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memcpy(base, (&except_vec_ejtag_debug - 1), 0x80);
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if (!cpu_has_veic) {
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void *base2 = (void *)(CAC_BASE + 0xa00);
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*((unsigned int *)base2) = 0x3c1a8000;
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*((unsigned int *)base2 + 1) = 0x375a0301;
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*((unsigned int *)base2 + 2) = 0x03400008;
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*((unsigned int *)base2 + 3) = 0x00000000;
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flush_icache_range((unsigned long)base2,
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(unsigned long)base2 + 0x10);
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}
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#else
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memcpy(base, &except_vec_ejtag_debug, 0x80);
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#endif
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flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
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}
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void __init prom_init(void)
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{
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board_nmi_handler_setup = mips_nmi_setup;
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board_ejtag_handler_setup = mips_ejtag_setup;
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fw_init_cmdline();
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#ifdef CONFIG_EARLY_PRINTK
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if ((strstr(fw_getcmdline(), "console=ttyS0")) != NULL)
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fw_init_early_console(0);
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else if ((strstr(fw_getcmdline(), "console=ttyS1")) != NULL)
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fw_init_early_console(1);
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#endif
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}
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void __init prom_free_prom_memory(void)
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{
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}
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