forked from Minki/linux
6a030ee36a
Commit 718a350 (ARM: i.MX51: Add PATA support) adds pata support to the
imx51.dtsi file and is using clock 161. The problem is that the right
clock is 172, according to commit 5d530bb (ARM: i.MX5: Add PATA and SRTC
clocks). Using the clock 172 makes things work again (and kills a nasty
system freeze).
Tested-by: Steev Klimaszewski <steev@gentoo.org>
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
821 lines
21 KiB
Plaintext
821 lines
21 KiB
Plaintext
/*
|
|
* Copyright 2011 Freescale Semiconductor, Inc.
|
|
* Copyright 2011 Linaro Ltd.
|
|
*
|
|
* The code contained herein is licensed under the GNU General Public
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
* Version 2 or later at the following locations:
|
|
*
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
#include "imx51-pinfunc.h"
|
|
|
|
/ {
|
|
aliases {
|
|
gpio0 = &gpio1;
|
|
gpio1 = &gpio2;
|
|
gpio2 = &gpio3;
|
|
gpio3 = &gpio4;
|
|
i2c0 = &i2c1;
|
|
i2c1 = &i2c2;
|
|
serial0 = &uart1;
|
|
serial1 = &uart2;
|
|
serial2 = &uart3;
|
|
spi0 = &ecspi1;
|
|
spi1 = &ecspi2;
|
|
spi2 = &cspi;
|
|
};
|
|
|
|
tzic: tz-interrupt-controller@e0000000 {
|
|
compatible = "fsl,imx51-tzic", "fsl,tzic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0xe0000000 0x4000>;
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ckil {
|
|
compatible = "fsl,imx-ckil", "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
ckih1 {
|
|
compatible = "fsl,imx-ckih1", "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
ckih2 {
|
|
compatible = "fsl,imx-ckih2", "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
osc {
|
|
compatible = "fsl,imx-osc", "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a8";
|
|
reg = <0>;
|
|
clock-latency = <61036>; /* two CLK32 periods */
|
|
clocks = <&clks 24>;
|
|
clock-names = "cpu";
|
|
operating-points = <
|
|
/* kHz uV (No regulator support) */
|
|
160000 0
|
|
800000 0
|
|
>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&tzic>;
|
|
ranges;
|
|
|
|
ipu: ipu@40000000 {
|
|
#crtc-cells = <1>;
|
|
compatible = "fsl,imx51-ipu";
|
|
reg = <0x40000000 0x20000000>;
|
|
interrupts = <11 10>;
|
|
clocks = <&clks 59>, <&clks 110>, <&clks 61>;
|
|
clock-names = "bus", "di0", "di1";
|
|
resets = <&src 2>;
|
|
};
|
|
|
|
aips@70000000 { /* AIPS1 */
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x70000000 0x10000000>;
|
|
ranges;
|
|
|
|
spba@70000000 {
|
|
compatible = "fsl,spba-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x70000000 0x40000>;
|
|
ranges;
|
|
|
|
esdhc1: esdhc@70004000 {
|
|
compatible = "fsl,imx51-esdhc";
|
|
reg = <0x70004000 0x4000>;
|
|
interrupts = <1>;
|
|
clocks = <&clks 44>, <&clks 0>, <&clks 71>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
esdhc2: esdhc@70008000 {
|
|
compatible = "fsl,imx51-esdhc";
|
|
reg = <0x70008000 0x4000>;
|
|
interrupts = <2>;
|
|
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@7000c000 {
|
|
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
|
reg = <0x7000c000 0x4000>;
|
|
interrupts = <33>;
|
|
clocks = <&clks 32>, <&clks 33>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi1: ecspi@70010000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx51-ecspi";
|
|
reg = <0x70010000 0x4000>;
|
|
interrupts = <36>;
|
|
clocks = <&clks 51>, <&clks 52>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi2: ssi@70014000 {
|
|
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
|
reg = <0x70014000 0x4000>;
|
|
interrupts = <30>;
|
|
clocks = <&clks 49>;
|
|
dmas = <&sdma 24 1 0>,
|
|
<&sdma 25 1 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
|
|
status = "disabled";
|
|
};
|
|
|
|
esdhc3: esdhc@70020000 {
|
|
compatible = "fsl,imx51-esdhc";
|
|
reg = <0x70020000 0x4000>;
|
|
interrupts = <3>;
|
|
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
esdhc4: esdhc@70024000 {
|
|
compatible = "fsl,imx51-esdhc";
|
|
reg = <0x70024000 0x4000>;
|
|
interrupts = <4>;
|
|
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usbphy0: usbphy@0 {
|
|
compatible = "usb-nop-xceiv";
|
|
clocks = <&clks 124>;
|
|
clock-names = "main_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
usbotg: usb@73f80000 {
|
|
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
|
reg = <0x73f80000 0x0200>;
|
|
interrupts = <18>;
|
|
clocks = <&clks 108>;
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
fsl,usbphy = <&usbphy0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh1: usb@73f80200 {
|
|
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
|
reg = <0x73f80200 0x0200>;
|
|
interrupts = <14>;
|
|
clocks = <&clks 108>;
|
|
fsl,usbmisc = <&usbmisc 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh2: usb@73f80400 {
|
|
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
|
reg = <0x73f80400 0x0200>;
|
|
interrupts = <16>;
|
|
clocks = <&clks 108>;
|
|
fsl,usbmisc = <&usbmisc 2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh3: usb@73f80600 {
|
|
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
|
reg = <0x73f80600 0x0200>;
|
|
interrupts = <17>;
|
|
clocks = <&clks 108>;
|
|
fsl,usbmisc = <&usbmisc 3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc: usbmisc@73f80800 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx51-usbmisc";
|
|
reg = <0x73f80800 0x200>;
|
|
clocks = <&clks 108>;
|
|
};
|
|
|
|
gpio1: gpio@73f84000 {
|
|
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
|
reg = <0x73f84000 0x4000>;
|
|
interrupts = <50 51>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@73f88000 {
|
|
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
|
reg = <0x73f88000 0x4000>;
|
|
interrupts = <52 53>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@73f8c000 {
|
|
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
|
reg = <0x73f8c000 0x4000>;
|
|
interrupts = <54 55>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@73f90000 {
|
|
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
|
reg = <0x73f90000 0x4000>;
|
|
interrupts = <56 57>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
kpp: kpp@73f94000 {
|
|
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
|
|
reg = <0x73f94000 0x4000>;
|
|
interrupts = <60>;
|
|
clocks = <&clks 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog1: wdog@73f98000 {
|
|
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
|
reg = <0x73f98000 0x4000>;
|
|
interrupts = <58>;
|
|
clocks = <&clks 0>;
|
|
};
|
|
|
|
wdog2: wdog@73f9c000 {
|
|
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
|
reg = <0x73f9c000 0x4000>;
|
|
interrupts = <59>;
|
|
clocks = <&clks 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpt: timer@73fa0000 {
|
|
compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
|
|
reg = <0x73fa0000 0x4000>;
|
|
interrupts = <39>;
|
|
clocks = <&clks 36>, <&clks 41>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
iomuxc: iomuxc@73fa8000 {
|
|
compatible = "fsl,imx51-iomuxc";
|
|
reg = <0x73fa8000 0x4000>;
|
|
};
|
|
|
|
pwm1: pwm@73fb4000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
|
|
reg = <0x73fb4000 0x4000>;
|
|
clocks = <&clks 37>, <&clks 38>;
|
|
clock-names = "ipg", "per";
|
|
interrupts = <61>;
|
|
};
|
|
|
|
pwm2: pwm@73fb8000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
|
|
reg = <0x73fb8000 0x4000>;
|
|
clocks = <&clks 39>, <&clks 40>;
|
|
clock-names = "ipg", "per";
|
|
interrupts = <94>;
|
|
};
|
|
|
|
uart1: serial@73fbc000 {
|
|
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
|
reg = <0x73fbc000 0x4000>;
|
|
interrupts = <31>;
|
|
clocks = <&clks 28>, <&clks 29>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@73fc0000 {
|
|
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
|
reg = <0x73fc0000 0x4000>;
|
|
interrupts = <32>;
|
|
clocks = <&clks 30>, <&clks 31>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
src: src@73fd0000 {
|
|
compatible = "fsl,imx51-src";
|
|
reg = <0x73fd0000 0x4000>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
clks: ccm@73fd4000{
|
|
compatible = "fsl,imx51-ccm";
|
|
reg = <0x73fd4000 0x4000>;
|
|
interrupts = <0 71 0x04 0 72 0x04>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
|
|
aips@80000000 { /* AIPS2 */
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x80000000 0x10000000>;
|
|
ranges;
|
|
|
|
iim: iim@83f98000 {
|
|
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
|
|
reg = <0x83f98000 0x4000>;
|
|
interrupts = <69>;
|
|
clocks = <&clks 107>;
|
|
};
|
|
|
|
ecspi2: ecspi@83fac000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx51-ecspi";
|
|
reg = <0x83fac000 0x4000>;
|
|
interrupts = <37>;
|
|
clocks = <&clks 53>, <&clks 54>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdma: sdma@83fb0000 {
|
|
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
|
|
reg = <0x83fb0000 0x4000>;
|
|
interrupts = <6>;
|
|
clocks = <&clks 56>, <&clks 56>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
|
};
|
|
|
|
cspi: cspi@83fc0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
|
|
reg = <0x83fc0000 0x4000>;
|
|
interrupts = <38>;
|
|
clocks = <&clks 55>, <&clks 55>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@83fc4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
|
|
reg = <0x83fc4000 0x4000>;
|
|
interrupts = <63>;
|
|
clocks = <&clks 35>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@83fc8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
|
|
reg = <0x83fc8000 0x4000>;
|
|
interrupts = <62>;
|
|
clocks = <&clks 34>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi1: ssi@83fcc000 {
|
|
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
|
reg = <0x83fcc000 0x4000>;
|
|
interrupts = <29>;
|
|
clocks = <&clks 48>;
|
|
dmas = <&sdma 28 0 0>,
|
|
<&sdma 29 0 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
|
status = "disabled";
|
|
};
|
|
|
|
audmux: audmux@83fd0000 {
|
|
compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
|
|
reg = <0x83fd0000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
weim: weim@83fda000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,imx51-weim";
|
|
reg = <0x83fda000 0x1000>;
|
|
clocks = <&clks 57>;
|
|
ranges = <
|
|
0 0 0xb0000000 0x08000000
|
|
1 0 0xb8000000 0x08000000
|
|
2 0 0xc0000000 0x08000000
|
|
3 0 0xc8000000 0x04000000
|
|
4 0 0xcc000000 0x02000000
|
|
5 0 0xce000000 0x02000000
|
|
>;
|
|
status = "disabled";
|
|
};
|
|
|
|
nfc: nand@83fdb000 {
|
|
compatible = "fsl,imx51-nand";
|
|
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
|
|
interrupts = <8>;
|
|
clocks = <&clks 60>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pata: pata@83fe0000 {
|
|
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
|
|
reg = <0x83fe0000 0x4000>;
|
|
interrupts = <70>;
|
|
clocks = <&clks 172>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi3: ssi@83fe8000 {
|
|
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
|
reg = <0x83fe8000 0x4000>;
|
|
interrupts = <96>;
|
|
clocks = <&clks 50>;
|
|
dmas = <&sdma 46 0 0>,
|
|
<&sdma 47 0 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
|
|
status = "disabled";
|
|
};
|
|
|
|
fec: ethernet@83fec000 {
|
|
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
|
|
reg = <0x83fec000 0x4000>;
|
|
interrupts = <87>;
|
|
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
|
|
clock-names = "ipg", "ahb", "ptp";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&iomuxc {
|
|
audmux {
|
|
pinctrl_audmux_1: audmuxgrp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
|
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
|
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
|
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
|
>;
|
|
};
|
|
};
|
|
|
|
fec {
|
|
pinctrl_fec_1: fecgrp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
|
|
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
|
|
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
|
|
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
|
|
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
|
|
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
|
|
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
|
|
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
|
|
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
|
|
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
|
|
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
|
|
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
|
|
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
|
|
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
|
|
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
|
|
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
|
|
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec_2: fecgrp-2 {
|
|
fsl,pins = <
|
|
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
|
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
|
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
|
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
|
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
|
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
|
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
|
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
|
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
|
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
|
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
|
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
|
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
|
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
|
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
|
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
|
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
|
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
|
>;
|
|
};
|
|
};
|
|
|
|
ecspi1 {
|
|
pinctrl_ecspi1_1: ecspi1grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
|
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
|
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
|
>;
|
|
};
|
|
};
|
|
|
|
ecspi2 {
|
|
pinctrl_ecspi2_1: ecspi2grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
|
|
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
|
|
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
|
|
>;
|
|
};
|
|
};
|
|
|
|
esdhc1 {
|
|
pinctrl_esdhc1_1: esdhc1grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
|
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
|
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
|
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
|
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
|
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
|
>;
|
|
};
|
|
};
|
|
|
|
esdhc2 {
|
|
pinctrl_esdhc2_1: esdhc2grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
|
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
|
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
|
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
|
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
|
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
|
>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
pinctrl_i2c2_1: i2c2grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
|
|
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_2: i2c2grp-2 {
|
|
fsl,pins = <
|
|
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
|
|
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_3: i2c2grp-3 {
|
|
fsl,pins = <
|
|
MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
|
|
MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
|
|
>;
|
|
};
|
|
};
|
|
|
|
ipu_disp1 {
|
|
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
|
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
|
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
|
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
|
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
|
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
|
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
|
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
|
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
|
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
|
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
|
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
|
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
|
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
|
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
|
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
|
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
|
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
|
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
|
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
|
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
|
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
|
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
|
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
|
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
|
|
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
|
|
>;
|
|
};
|
|
};
|
|
|
|
ipu_disp2 {
|
|
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
|
|
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
|
|
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
|
|
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
|
|
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
|
|
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
|
|
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
|
|
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
|
|
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
|
|
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
|
|
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
|
|
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
|
|
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
|
|
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
|
|
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
|
|
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
|
|
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
|
|
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
|
|
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
|
|
MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
|
|
>;
|
|
};
|
|
};
|
|
|
|
kpp {
|
|
pinctrl_kpp_1: kppgrp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
|
|
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
|
|
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
|
|
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
|
|
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
|
|
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
|
|
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
|
|
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
|
|
>;
|
|
};
|
|
};
|
|
|
|
pata {
|
|
pinctrl_pata_1: patagrp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
|
|
MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
|
|
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
|
|
MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
|
|
MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
|
|
MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
|
|
MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
|
|
MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
|
|
MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
|
|
MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
|
|
MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
|
|
MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
|
|
MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
|
|
MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
|
|
MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
|
|
MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
|
|
MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
|
|
MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
|
|
MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
|
|
MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
|
|
MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
|
|
MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
|
|
MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
|
|
MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
|
|
MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
|
|
MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
|
|
MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
|
|
MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
|
|
MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
|
|
>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
pinctrl_uart1_1: uart1grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
|
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
|
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
|
|
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
|
|
>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
pinctrl_uart2_1: uart2grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
|
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
|
>;
|
|
};
|
|
};
|
|
|
|
uart3 {
|
|
pinctrl_uart3_1: uart3grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
|
|
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
|
|
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
|
|
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3_2: uart3grp-2 {
|
|
fsl,pins = <
|
|
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
|
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
|
>;
|
|
};
|
|
};
|
|
|
|
usbh1 {
|
|
pinctrl_usbh1_1: usbh1grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
|
|
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
|
|
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
|
|
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
|
|
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
|
|
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
|
|
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
|
|
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
|
|
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
|
|
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
|
|
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
|
|
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
|
|
>;
|
|
};
|
|
};
|
|
|
|
usbh2 {
|
|
pinctrl_usbh2_1: usbh2grp-1 {
|
|
fsl,pins = <
|
|
MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
|
|
MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
|
|
MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
|
|
MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
|
|
MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
|
|
MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
|
|
MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
|
|
MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
|
|
MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
|
|
MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
|
|
MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
|
|
MX51_PAD_EIM_A26__USBH2_STP 0x1e5
|
|
>;
|
|
};
|
|
};
|
|
};
|