forked from Minki/linux
4fb2847437
Instruction fault status register, IFSR, was introduced on ARMv6 to
provide status information about the last insturction fault. It
needed for proper prefetch abort handling.
Now we have three prefetch abort model:
* legacy - for CPUs before ARMv6. They doesn't provide neither
IFSR nor IFAR. We simulate IFSR with section translation fault
status for them to generalize code;
* ARMv6 - provides IFSR, but not IFAR;
* ARMv7 - provides both IFSR and IFAR.
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
372 lines
9.4 KiB
ArmAsm
372 lines
9.4 KiB
ArmAsm
/*
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* linux/arch/arm/mm/arm940.S: utility functions for ARM940T
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*
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* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
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#define CACHE_DLINESIZE 16
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#define CACHE_DSEGMENTS 4
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#define CACHE_DENTRIES 64
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.text
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/*
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* cpu_arm940_proc_init()
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* cpu_arm940_switch_mm()
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*
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* These are not required.
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*/
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ENTRY(cpu_arm940_proc_init)
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ENTRY(cpu_arm940_switch_mm)
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mov pc, lr
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/*
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* cpu_arm940_proc_fin()
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*/
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ENTRY(cpu_arm940_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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bl arm940_flush_kern_cache_all
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x00001000 @ i-cache
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bic r0, r0, #0x00000004 @ d-cache
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldmfd sp!, {pc}
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/*
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* cpu_arm940_reset(loc)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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ENTRY(cpu_arm940_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ flush I cache
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x00000005 @ .............c.p
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bic ip, ip, #0x00001000 @ i-cache
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_arm940_do_idle()
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*/
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.align 5
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ENTRY(cpu_arm940_do_idle)
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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/*
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* flush_user_cache_all()
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*/
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ENTRY(arm940_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(arm940_flush_kern_cache_all)
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mov r2, #VM_EXEC
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/* FALLTHROUGH */
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* There is no efficient way to flush a range of cache entries
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* in the specified address range. Thus, flushes all.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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ENTRY(arm940_flush_user_cache_range)
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mov ip, #0
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache
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#else
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 3 to 0
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#endif
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_coherent_user_range)
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/* FALLTHROUGH */
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - page aligned address
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*/
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ENTRY(arm940_flush_kern_dcache_page)
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mov ip, #0
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* There is no efficient way to invalidate a specifid virtual
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* address range. Thus, invalidates all.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_dma_inv_range)
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mov ip, #0
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* There is no efficient way to clean a specifid virtual
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* address range. Thus, cleans all.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_dma_clean_range)
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ENTRY(cpu_arm940_dcache_clean_area)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* There is no efficient way to clean and invalidate a specifid
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* virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_dma_flush_range)
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mov ip, #0
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
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#else
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mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
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#endif
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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ENTRY(arm940_cache_fns)
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.long arm940_flush_kern_cache_all
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.long arm940_flush_user_cache_all
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.long arm940_flush_user_cache_range
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.long arm940_coherent_kern_range
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.long arm940_coherent_user_range
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.long arm940_flush_kern_dcache_page
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.long arm940_dma_inv_range
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.long arm940_dma_clean_range
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.long arm940_dma_flush_range
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__INIT
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.type __arm940_setup, #function
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__arm940_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
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mcr p15, 0, r0, c6, c4, 0
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mcr p15, 0, r0, c6, c5, 0
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mcr p15, 0, r0, c6, c6, 0
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mcr p15, 0, r0, c6, c7, 0
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mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
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mcr p15, 0, r0, c6, c4, 1
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mcr p15, 0, r0, c6, c5, 1
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mcr p15, 0, r0, c6, c6, 1
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mcr p15, 0, r0, c6, c7, 1
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mov r0, #0x0000003F @ base = 0, size = 4GB
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mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
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mcr p15, 0, r0, c6, c0, 1
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ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
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ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
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mcr p15, 0, r0, c6, c1, 1
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ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
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ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
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mcr p15, 0, r0, c6, c2, 1
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mov r0, #0x06
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mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
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mcr p15, 0, r0, c2, c0, 1
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r0, #0x00 @ disable whole write buffer
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#else
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mov r0, #0x02 @ Region 1 write bufferred
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#endif
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mcr p15, 0, r0, c3, c0, 0
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mov r0, #0x10000
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sub r0, r0, #1 @ r0 = 0xffff
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mcr p15, 0, r0, c5, c0, 0 @ all read/write access
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mcr p15, 0, r0, c5, c0, 1
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mrc p15, 0, r0, c1, c0 @ get control register
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orr r0, r0, #0x00001000 @ I-cache
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orr r0, r0, #0x00000005 @ MPU/D-cache
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mov pc, lr
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.size __arm940_setup, . - __arm940_setup
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__INITDATA
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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.type arm940_processor_functions, #object
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ENTRY(arm940_processor_functions)
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.word nommu_early_abort
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.word legacy_pabort
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.word cpu_arm940_proc_init
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.word cpu_arm940_proc_fin
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.word cpu_arm940_reset
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.word cpu_arm940_do_idle
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.word cpu_arm940_dcache_clean_area
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.word cpu_arm940_switch_mm
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.word 0 @ cpu_*_set_pte
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.size arm940_processor_functions, . - arm940_processor_functions
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.section ".rodata"
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.type cpu_arch_name, #object
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cpu_arch_name:
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.asciz "armv4t"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name:
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.asciz "v4"
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.size cpu_elf_name, . - cpu_elf_name
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.type cpu_arm940_name, #object
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cpu_arm940_name:
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.ascii "ARM940T"
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.size cpu_arm940_name, . - cpu_arm940_name
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.align
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.section ".proc.info.init", #alloc, #execinstr
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.type __arm940_proc_info,#object
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__arm940_proc_info:
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.long 0x41009400
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.long 0xff00fff0
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.long 0
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b __arm940_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
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.long cpu_arm940_name
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.long arm940_processor_functions
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.long 0
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.long 0
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.long arm940_cache_fns
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.size __arm940_proc_info, . - __arm940_proc_info
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