bc0ee9d24a
This patch does the plumbing required to invoke the V7M cache code added in earlier patches in this series, although there is no users for that yet. In order to honour the I/D cache disable config options, this patch changes the mechanism by which the CCR is set on boot, to be more like V7A/R. Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Tested-by: Andras Szemzo <sza@esh.hu> Tested-by: Joachim Eastwood <manabian@gmail.com> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
155 lines
3.8 KiB
ArmAsm
155 lines
3.8 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-v7m.S
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*
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* Copyright (C) 2008 ARM Ltd.
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv7-M processor support.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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#include <asm/v7m.h>
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#include "proc-macros.S"
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ENTRY(cpu_v7m_proc_init)
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ret lr
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ENDPROC(cpu_v7m_proc_init)
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ENTRY(cpu_v7m_proc_fin)
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ret lr
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ENDPROC(cpu_v7m_proc_fin)
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/*
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* cpu_v7m_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_v7m_reset)
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ret r0
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ENDPROC(cpu_v7m_reset)
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/*
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* cpu_v7m_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v7m_do_idle)
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wfi
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ret lr
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ENDPROC(cpu_v7m_do_idle)
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ENTRY(cpu_v7m_dcache_clean_area)
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ret lr
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ENDPROC(cpu_v7m_dcache_clean_area)
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/*
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* There is no MMU, so here is nothing to do.
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*/
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ENTRY(cpu_v7m_switch_mm)
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ret lr
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ENDPROC(cpu_v7m_switch_mm)
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.globl cpu_v7m_suspend_size
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.equ cpu_v7m_suspend_size, 0
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_v7m_do_suspend)
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ret lr
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ENDPROC(cpu_v7m_do_suspend)
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ENTRY(cpu_v7m_do_resume)
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ret lr
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ENDPROC(cpu_v7m_do_resume)
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#endif
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.section ".text.init", #alloc, #execinstr
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/*
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* __v7m_setup
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*
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* This should be able to cover all ARMv7-M cores.
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*/
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__v7m_setup:
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@ Configure the vector table base address
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ldr r0, =BASEADDR_V7M_SCB
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ldr r12, =vector_table
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str r12, [r0, V7M_SCB_VTOR]
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@ enable UsageFault, BusFault and MemManage fault.
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ldr r5, [r0, #V7M_SCB_SHCSR]
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orr r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
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str r5, [r0, #V7M_SCB_SHCSR]
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@ Lower the priority of the SVC and PendSV exceptions
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mov r5, #0x80000000
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str r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
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mov r5, #0x00800000
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str r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
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@ SVC to switch to handler mode. Notice that this requires sp to
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@ point to writeable memory because the processor saves
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@ some registers to the stack.
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badr r1, 1f
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ldr r5, [r12, #11 * 4] @ read the SVC vector entry
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str r1, [r12, #11 * 4] @ write the temporary SVC vector entry
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mov r6, lr @ save LR
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ldr sp, =init_thread_union + THREAD_START_SP
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cpsie i
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svc #0
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1: cpsid i
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str r5, [r12, #11 * 4] @ restore the original SVC vector entry
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mov lr, r6 @ restore LR
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@ Special-purpose control register
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mov r1, #1
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msr control, r1 @ Thread mode has unpriviledged access
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@ Configure the System Control Register to ensure 8-byte stack alignment
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@ Note the STKALIGN bit is either RW or RAO.
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ldr r0, [r0, V7M_SCB_CCR] @ system control register
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orr r0, #V7M_SCB_CCR_STKALIGN
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ret lr
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ENDPROC(__v7m_setup)
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define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
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.section ".rodata"
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string cpu_arch_name, "armv7m"
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string cpu_elf_name "v7m"
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string cpu_v7m_name "ARMv7-M"
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.section ".proc.info.init", #alloc
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/*
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* Match any ARMv7-M processor core.
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*/
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.type __v7m_proc_info, #object
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__v7m_proc_info:
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.long 0x000f0000 @ Required ID value
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.long 0x000f0000 @ Mask for ID
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.long 0 @ proc_info_list.__cpu_mm_mmu_flags
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.long 0 @ proc_info_list.__cpu_io_mmu_flags
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initfn __v7m_setup, __v7m_proc_info @ proc_info_list.__cpu_flush
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
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.long cpu_v7m_name
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.long v7m_processor_functions @ proc_info_list.proc
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.long 0 @ proc_info_list.tlb
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.long 0 @ proc_info_list.user
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.long nop_cache_fns @ proc_info_list.cache
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.size __v7m_proc_info, . - __v7m_proc_info
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