145b0a5d18
This patch add support for s3c2410/s3c2416/s3c2440/s3c2443 ADC. The s3c24xx is alomost same as ADCv1. But, There are a little difference as following: - ADCMUX register address - ADCDAT mask (10 bit or 12 bit ADC resolution according to SoC version) - s3c24xx/s3c64xx has not included ADC_PHY enable register Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
94 lines
2.9 KiB
Plaintext
94 lines
2.9 KiB
Plaintext
Samsung Exynos Analog to Digital Converter bindings
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The devicetree bindings are for the new ADC driver written for
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Exynos4 and upward SoCs from Samsung.
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New driver handles the following
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1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
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and future SoCs from Samsung
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2. Add ADC driver under iio/adc framework
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3. Also adds the Documentation for device tree bindings
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Required properties:
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- compatible: Must be "samsung,exynos-adc-v1"
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for exynos4412/5250 and s5pv210 controllers.
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Must be "samsung,exynos-adc-v2" for
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future controllers.
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Must be "samsung,exynos3250-adc" for
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controllers compatible with ADC of Exynos3250.
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Must be "samsung,s3c2410-adc" for
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the ADC in s3c2410 and compatibles
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Must be "samsung,s3c2416-adc" for
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the ADC in s3c2416 and compatibles
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Must be "samsung,s3c2440-adc" for
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the ADC in s3c2440 and compatibles
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Must be "samsung,s3c2443-adc" for
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the ADC in s3c2443 and compatibles
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Must be "samsung,s3c6410-adc" for
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the ADC in s3c6410 and compatibles
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- reg: List of ADC register address range
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- The base address and range of ADC register
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- The base address and range of ADC_PHY register (every
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SoC except for s3c24xx/s3c64xx ADC)
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- interrupts: Contains the interrupt information for the timer. The
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format is being dependent on which interrupt controller
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the Samsung device uses.
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- #io-channel-cells = <1>; As ADC has multiple outputs
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- clocks From common clock bindings: handles to clocks specified
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in "clock-names" property, in the same order.
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- clock-names From common clock bindings: list of clock input names
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used by ADC block:
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- "adc" : ADC bus clock
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- "sclk" : ADC special clock (only for Exynos3250 and
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compatible ADC block)
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- vdd-supply VDD input supply.
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Note: child nodes can be added for auto probing from device tree.
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Example: adding device info in dtsi file
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adc: adc@12D10000 {
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compatible = "samsung,exynos-adc-v1";
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reg = <0x12D10000 0x100>, <0x10040718 0x4>;
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interrupts = <0 106 0>;
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#io-channel-cells = <1>;
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io-channel-ranges;
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clocks = <&clock 303>;
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clock-names = "adc";
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vdd-supply = <&buck5_reg>;
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};
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Example: adding device info in dtsi file for Exynos3250 with additional sclk
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adc: adc@126C0000 {
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compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
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reg = <0x126C0000 0x100>, <0x10020718 0x4>;
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interrupts = <0 137 0>;
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#io-channel-cells = <1>;
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io-channel-ranges;
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clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
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clock-names = "adc", "sclk";
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vdd-supply = <&buck5_reg>;
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};
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Example: Adding child nodes in dts file
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adc@12D10000 {
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/* NTC thermistor is a hwmon device */
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ncp15wb473@0 {
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compatible = "murata,ncp15wb473";
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pullup-uv = <1800000>;
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pullup-ohm = <47000>;
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pulldown-ohm = <0>;
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io-channels = <&adc 4>;
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};
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};
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Note: Does not apply to ADC driver under arch/arm/plat-samsung/
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Note: The child node can be added under the adc node or separately.
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