b8c3f9b554
Use the new SYM_DATA, SYM_DATA_START, and SYM_DATA_END* macros for data,
so that the data in the object file look sane:
Value Size Type Bind Vis Ndx Name
0000 10 OBJECT GLOBAL DEFAULT 3 efi32_boot_gdt
000a 10 OBJECT LOCAL DEFAULT 3 save_gdt
0014 8 OBJECT LOCAL DEFAULT 3 func_rt_ptr
001c 48 OBJECT GLOBAL DEFAULT 3 efi_gdt64
004c 0 OBJECT LOCAL DEFAULT 3 efi_gdt64_end
0000 48 OBJECT LOCAL DEFAULT 3 gdt
0030 0 OBJECT LOCAL DEFAULT 3 gdt_end
0030 8 OBJECT LOCAL DEFAULT 3 efi_config
0038 49 OBJECT GLOBAL DEFAULT 3 efi32_config
0069 49 OBJECT GLOBAL DEFAULT 3 efi64_config
All have correct size and type now.
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Cao jin <caoj.fnst@cn.fujitsu.com>
Cc: Enrico Weigelt <info@metux.net>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kate Stewart <kstewart@linuxfoundation.org>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: linux-arch@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Wei Huang <wei@redhat.com>
Cc: x86-ml <x86@kernel.org>
Cc: Xiaoyao Li <xiaoyao.li@linux.intel.com>
Link: https://lkml.kernel.org/r/20191011115108.12392-13-jslaby@suse.cz
101 lines
1.9 KiB
ArmAsm
101 lines
1.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AMD Memory Encryption Support
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*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*/
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#include <linux/linkage.h>
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#include <asm/processor-flags.h>
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#include <asm/msr.h>
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#include <asm/asm-offsets.h>
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.text
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.code32
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ENTRY(get_sev_encryption_bit)
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xor %eax, %eax
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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push %ebx
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push %ecx
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push %edx
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/* Check if running under a hypervisor */
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movl $1, %eax
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cpuid
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bt $31, %ecx /* Check the hypervisor bit */
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jnc .Lno_sev
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movl $0x80000000, %eax /* CPUID to check the highest leaf */
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cpuid
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cmpl $0x8000001f, %eax /* See if 0x8000001f is available */
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jb .Lno_sev
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/*
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* Check for the SEV feature:
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* CPUID Fn8000_001F[EAX] - Bit 1
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* CPUID Fn8000_001F[EBX] - Bits 5:0
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* Pagetable bit position used to indicate encryption
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*/
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movl $0x8000001f, %eax
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cpuid
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bt $1, %eax /* Check if SEV is available */
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jnc .Lno_sev
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movl $MSR_AMD64_SEV, %ecx /* Read the SEV MSR */
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rdmsr
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bt $MSR_AMD64_SEV_ENABLED_BIT, %eax /* Check if SEV is active */
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jnc .Lno_sev
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movl %ebx, %eax
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andl $0x3f, %eax /* Return the encryption bit location */
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jmp .Lsev_exit
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.Lno_sev:
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xor %eax, %eax
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.Lsev_exit:
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pop %edx
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pop %ecx
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pop %ebx
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#endif /* CONFIG_AMD_MEM_ENCRYPT */
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ret
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ENDPROC(get_sev_encryption_bit)
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.code64
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ENTRY(set_sev_encryption_mask)
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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push %rbp
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push %rdx
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movq %rsp, %rbp /* Save current stack pointer */
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call get_sev_encryption_bit /* Get the encryption bit position */
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testl %eax, %eax
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jz .Lno_sev_mask
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bts %rax, sme_me_mask(%rip) /* Create the encryption mask */
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.Lno_sev_mask:
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movq %rbp, %rsp /* Restore original stack pointer */
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pop %rdx
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pop %rbp
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#endif
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xor %rax, %rax
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ret
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ENDPROC(set_sev_encryption_mask)
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.data
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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.balign 8
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SYM_DATA(sme_me_mask, .quad 0)
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#endif
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