b8bf04e1fd
Shorter device name, match Tegra and our existing enums. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
64 lines
2.3 KiB
C
64 lines
2.3 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "ctxnvc0.h"
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static const struct nvc0_gr_pack
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gk20a_grctx_pack_mthd[] = {
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{ nve4_grctx_init_a097_0, 0xa297 },
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{ nvc0_grctx_init_902d_0, 0x902d },
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{}
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};
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struct nouveau_oclass *
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gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
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.base.handle = NV_ENGCTX(GR, 0xea),
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.base.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nvc0_gr_context_ctor,
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.dtor = nvc0_gr_context_dtor,
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.init = _nouveau_gr_context_init,
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.fini = _nouveau_gr_context_fini,
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.rd32 = _nouveau_gr_context_rd32,
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.wr32 = _nouveau_gr_context_wr32,
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},
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.main = nve4_grctx_generate_main,
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.unkn = nve4_grctx_generate_unkn,
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.hub = nve4_grctx_pack_hub,
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.gpc = nve4_grctx_pack_gpc,
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.zcull = nvc0_grctx_pack_zcull,
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.tpc = nve4_grctx_pack_tpc,
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.ppc = nve4_grctx_pack_ppc,
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.icmd = nve4_grctx_pack_icmd,
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.mthd = gk20a_grctx_pack_mthd,
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.bundle = nve4_grctx_generate_bundle,
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.bundle_size = 0x1800,
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.bundle_min_gpm_fifo_depth = 0x62,
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.bundle_token_limit = 0x100,
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.pagepool = nve4_grctx_generate_pagepool,
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.pagepool_size = 0x8000,
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.attrib = nvd7_grctx_generate_attrib,
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.attrib_nr_max = 0x240,
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.attrib_nr = 0x240,
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.alpha_nr_max = 0x648 + (0x648 / 2),
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.alpha_nr = 0x648,
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}.base;
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