b8a0330239
ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for kernel proper. SMP barrier is provided by DMB instruction which also guarantees local barrier hence used as backend of smp_*mb() as well as *mb() APIs Also hookup barriers into MMIO accessors to avoid ordering issues in IO Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
144 lines
3.3 KiB
C
144 lines
3.3 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_IO_H
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#define _ASM_ARC_IO_H
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <asm/page.h>
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extern void __iomem *ioremap(unsigned long physaddr, unsigned long size);
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extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
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unsigned long flags);
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extern void iounmap(const void __iomem *addr);
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#define ioremap_nocache(phy, sz) ioremap(phy, sz)
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#define ioremap_wc(phy, sz) ioremap(phy, sz)
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/* Change struct page to physical address */
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#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 b;
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__asm__ __volatile__(
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" ldb%U1 %0, %1 \n"
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: "=r" (b)
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: "m" (*(volatile u8 __force *)addr)
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: "memory");
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return b;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 s;
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__asm__ __volatile__(
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" ldw%U1 %0, %1 \n"
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: "=r" (s)
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: "m" (*(volatile u16 __force *)addr)
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: "memory");
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return s;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 w;
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__asm__ __volatile__(
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" ld%U1 %0, %1 \n"
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: "=r" (w)
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: "m" (*(volatile u32 __force *)addr)
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: "memory");
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return w;
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}
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
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{
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__asm__ __volatile__(
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" stb%U1 %0, %1 \n"
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:
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: "r" (b), "m" (*(volatile u8 __force *)addr)
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: "memory");
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 s, volatile void __iomem *addr)
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{
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__asm__ __volatile__(
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" stw%U1 %0, %1 \n"
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:
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: "r" (s), "m" (*(volatile u16 __force *)addr)
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: "memory");
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 w, volatile void __iomem *addr)
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{
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__asm__ __volatile__(
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" st%U1 %0, %1 \n"
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:
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: "r" (w), "m" (*(volatile u32 __force *)addr)
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: "memory");
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}
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#ifdef CONFIG_ISA_ARCV2
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#include <asm/barrier.h>
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#else
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#define __iormb() do { } while (0)
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#define __iowmb() do { } while (0)
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#endif
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/*
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* MMIO can also get buffered/optimized in micro-arch, so barriers needed
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* Based on ARM model for the typical use case
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*
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* <ST [DMA buffer]>
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* <writel MMIO "go" reg>
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* or:
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* <readl MMIO "status" reg>
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* <LD [DMA buffer]>
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*
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* http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
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*/
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
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/*
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* Relaxed API for drivers which can handle any ordering themselves
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*/
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#define readb_relaxed(c) __raw_readb(c)
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#define readw_relaxed(c) __raw_readw(c)
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#define readl_relaxed(c) __raw_readl(c)
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#define writeb_relaxed(v,c) __raw_writeb(v,c)
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#define writew_relaxed(v,c) __raw_writew(v,c)
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#define writel_relaxed(v,c) __raw_writel(v,c)
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#include <asm-generic/io.h>
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#endif /* _ASM_ARC_IO_H */
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