b82b6cca48
The only place where the time is invalid is when the ACPI_CSTATE_FFH entry method is not set. Otherwise for all the drivers, the time can be correctly measured. Instead of duplicating the CPUIDLE_FLAG_TIME_VALID flag in all the drivers for all the states, just invert the logic by replacing it by the flag CPUIDLE_FLAG_TIME_INVALID, hence we can set this flag only for the acpi idle driver, remove the former flag from all the drivers and invert the logic with this flag in the different governor. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
/*
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* CPU idle for DaVinci SoCs
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*
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* Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
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*
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* Derived from Marvell Kirkwood CPU idle code
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* (arch/arm/mach-kirkwood/cpuidle.c)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/cpuidle.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <asm/proc-fns.h>
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#include <asm/cpuidle.h>
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#include <mach/cpuidle.h>
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#include <mach/ddr2.h>
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#define DAVINCI_CPUIDLE_MAX_STATES 2
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static void __iomem *ddr2_reg_base;
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static bool ddr2_pdown;
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static void davinci_save_ddr_power(int enter, bool pdown)
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{
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u32 val;
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val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
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if (enter) {
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if (pdown)
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val |= DDR2_SRPD_BIT;
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else
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val &= ~DDR2_SRPD_BIT;
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val |= DDR2_LPMODEN_BIT;
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} else {
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val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
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}
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__raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
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}
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/* Actual code that puts the SoC in different idle states */
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static int davinci_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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davinci_save_ddr_power(1, ddr2_pdown);
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cpu_do_idle();
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davinci_save_ddr_power(0, ddr2_pdown);
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return index;
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}
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static struct cpuidle_driver davinci_idle_driver = {
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.name = "cpuidle-davinci",
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.owner = THIS_MODULE,
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.states[0] = ARM_CPUIDLE_WFI_STATE,
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.states[1] = {
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.enter = davinci_enter_idle,
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.exit_latency = 10,
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.target_residency = 10000,
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.name = "DDR SR",
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.desc = "WFI and DDR Self Refresh",
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},
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.state_count = DAVINCI_CPUIDLE_MAX_STATES,
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};
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static int __init davinci_cpuidle_probe(struct platform_device *pdev)
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{
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struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
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if (!pdata) {
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dev_err(&pdev->dev, "cannot get platform data\n");
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return -ENOENT;
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}
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ddr2_reg_base = pdata->ddr2_ctlr_base;
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ddr2_pdown = pdata->ddr2_pdown;
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return cpuidle_register(&davinci_idle_driver, NULL);
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}
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static struct platform_driver davinci_cpuidle_driver = {
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.driver = {
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.name = "cpuidle-davinci",
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.owner = THIS_MODULE,
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},
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};
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static int __init davinci_cpuidle_init(void)
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{
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return platform_driver_probe(&davinci_cpuidle_driver,
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davinci_cpuidle_probe);
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}
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device_initcall(davinci_cpuidle_init);
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