forked from Minki/linux
e355e0f684
imx6ul-pico has WDOG1_B pin connected to the PMIC. Pass the 'fsl,ext-reset-output' property so that the watchdog can trigger a system POR reset via PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
550 lines
13 KiB
Plaintext
550 lines
13 KiB
Plaintext
/*
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* Copyright 2015 Technexion Ltd.
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*
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* Author: Wig Cheng <wig.cheng@technexion.com>
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* Richard Hu <richard.hu@technexion.com>
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* Tapani Utriainen <tapani@technexion.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "imx6ul.dtsi"
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/ {
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model = "Technexion Pico i.MX6UL Board";
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compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
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memory {
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reg = <0x80000000 0x10000000>;
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};
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chosen {
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stdout-path = &uart6;
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm3 0 5000000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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status = "okay";
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};
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reg_2p5v: regulator-2p5v {
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compatible = "regulator-fixed";
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regulator-name = "2P5V";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_sd1_vmmc: regulator-sd1-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg_vbus: regulator-usb-otg-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 6 0>;
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};
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reg_brcm: regulator-brcm {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_brcm_reg>;
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regulator-name = "brcm_reg";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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startup-delay-us = <200000>;
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};
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sound {
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compatible = "fsl,imx-audio-sgtl5000";
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model = "imx6ul-sgtl5000";
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audio-cpu = <&sai1>;
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audio-codec = <&codec>;
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audio-routing =
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"LINE_IN", "Line In Jack",
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HP_OUT";
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};
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sys_mclk: clock-sys-mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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leds {
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compatible = "gpio-leds";
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hobbitled {
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label = "hobbitled";
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gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "okay";
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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max-speed = <100>;
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interrupt-parent = <&gpio5>;
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interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: pfuze3000@08 {
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compatible = "fsl,pfuze3000";
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reg = <0x08>;
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regulators {
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/* VDD_ARM_SOC_IN*/
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sw1b_reg: sw1b {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* DRAM */
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sw3a_reg: sw3 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* DRAM */
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&i2c2 {
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clock_frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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codec: sgtl5000@0a {
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reg = <0x0a>;
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compatible = "fsl,sgtl5000";
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clocks = <&sys_mclk>;
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VDDA-supply = <®_2p5v>;
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VDDIO-supply = <®_3p3v>;
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};
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};
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&i2c3 {
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clock_frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&lcdif {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
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display = <&display0>;
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status = "okay";
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display0: display0 {
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bits-per-pixel = <32>;
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bus-width = <24>;
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <33200000>;
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hactive = <800>;
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vactive = <480>;
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hfront-porch = <210>;
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hback-porch = <46>;
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hsync-len = <1>;
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vback-porch = <22>;
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vfront-porch = <23>;
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vsync-len = <1>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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};
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};
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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status = "okay";
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};
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&pwm7 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm7>;
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status = "okay";
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};
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&pwm8 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm8>;
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status = "okay";
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};
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&sai1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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uart-has-rtscts;
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status = "okay";
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};
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&uart6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart6>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1_id>;
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dr_mode = "otg";
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disable-over-current;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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keep-power-in-suspend;
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status = "okay";
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};
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&usdhc2 { /* Wifi SDIO */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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no-1-8-v;
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non-removable;
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keep-power-in-suspend;
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wakeup-source;
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vmmc-supply = <®_brcm>;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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};
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&iomuxc {
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pinctrl_brcm_reg: brcmreggrp {
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fsl,pins = <
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MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
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MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
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MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
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MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
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MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
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MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
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MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
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MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
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>;
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};
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pinctrl_lcdif_dat: lcdifdatgrp {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
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MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
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MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
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MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
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MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
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MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
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MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
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MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
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MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
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MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
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MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
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MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
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MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
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MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
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MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
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MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
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MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
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MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
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MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
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MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
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MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
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MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
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MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
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MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
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>;
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};
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pinctrl_lcdif_ctrl: lcdifctrlgrp {
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fsl,pins = <
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MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
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MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
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MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
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MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
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/* LCD reset */
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MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
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>;
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};
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pinctrl_pwm3: pwm3grp {
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fsl,pins = <
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MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
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>;
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};
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pinctrl_pwm7: pwm7grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
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>;
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};
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pinctrl_pwm8: pwm8grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
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>;
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};
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pinctrl_sai1: sai1grp {
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fsl,pins = <
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MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
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MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
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MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
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MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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|
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
|
|
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
|
|
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
|
|
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5: uart5grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
|
|
MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
|
|
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
|
|
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart6: uart6grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
|
|
MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usb_otg1: usbotg1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usb_otg1_id: usbotg1idgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
|
MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
|
|
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
|
|
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
|
|
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
|
|
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
|
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
|
|
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
|
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
|
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
|
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
|
|
>;
|
|
};
|
|
};
|