Jayachandran C b66f953cd0 MIPS: Netlogic: Avoid unnecessary cache flushes ... XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache flushes. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2011-12-07 22:04:54 +00:00
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cpu-feature-overrides.h	MIPS: Netlogic: Avoid unnecessary cache flushes	2011-12-07 22:04:54 +00:00
irq.h
war.h