Paul Hsieh 7fc5c319ef drm/amd/display: dmcu wait loop calculation is incorrect in RV ... [Why] Driver already get display clock from SMU base on MHz, but driver read again and mutiple 1000 cause wait loop value is overflow. [How] remove coding error Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-04-22 18:11:48 -04:00
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dce100	drm/amd/display: remove redundant assignment to variable dp_ref_clk_khz	2020-04-22 18:11:45 -04:00
dce110	drm/amdgpu/display: fix 64 bit divide	2019-10-03 09:11:00 -05:00
dce112	drm/amd/display: rename core_dc to dc	2019-12-05 16:26:39 -05:00
dce120	drm/amd/display: Copy max_clks_by_state after dce_clk_mgr_construct	2019-07-18 14:18:09 -05:00
dcn10	drm/amd/display: dmcu wait loop calculation is incorrect in RV	2020-04-22 18:11:48 -04:00
dcn20	drm/amd/display: DPP DTO isn't update properly.	2020-03-19 00:03:04 -04:00
dcn21	drm/amd/display: Check for null fclk voltage when parsing clock table	2020-04-09 10:43:17 -04:00
clk_mgr.c	drm/amd/display: Unify psr feature flags	2020-04-22 18:11:47 -04:00
Makefile	amdgpu: Prevent build errors regarding soft/hard-float FP ABI tags	2020-02-11 15:35:22 -05:00