Thierry Reding 8a8005e3e1 drm/tegra: dpaux: Registers are 32-bit ...

Use a sized unsigned 32-bit data type (u32) to store register contents.
The DPAUX registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>

2015-06-12 16:26:04 +02:00

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