Florian Fainelli b4b32e3216 soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings ... In order to achieve expected MCP bus throughput on 3 particular chips: 7268, 7271 and 7278, do the appropriate programming of the MCP interface: increase number of MCP write credits, turn on write-back throttling when present. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>		2017-12-20 17:37:43 -08:00
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pm	soc bcm: brcmstb: Add support for S2/S3/S5 suspend states (MIPS)	2017-09-25 11:47:14 -07:00
biuctrl.c	soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings	2017-12-20 17:37:43 -08:00
common.c	soc: brcmstb: Add Product ID and Family ID helper functions	2017-10-03 11:54:54 +05:30
Kconfig	soc bcm: brcmstb: Add support for S2/S3/S5 suspend states (MIPS)	2017-09-25 11:47:14 -07:00
Makefile	soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)	2017-09-25 11:46:48 -07:00