forked from Minki/linux
b3df895aeb
This adds support kexec on FSL-BookE where the MMU can not be simply switched off. The code borrows the initial MMU-setup code to create the identical mapping mapping. The only difference to the original boot code is the size of the mapping(s) and the executeable address. The kexec code maps the first 2 GiB of memory in 256 MiB steps. This should work also on e500v1 boxes. SMP support is still not available. (Kumar: Added minor change to build to ifdef CONFIG_PPC_STD_MMU_64 some code that was PPC64 specific) Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
827 lines
16 KiB
ArmAsm
827 lines
16 KiB
ArmAsm
/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* kexec bits:
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* Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
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* GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor.h>
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#include <asm/kexec.h>
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#include <asm/bug.h>
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.text
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#ifdef CONFIG_IRQSTACKS
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_GLOBAL(call_do_softirq)
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mflr r0
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stw r0,4(r1)
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stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
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mr r1,r3
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bl __do_softirq
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lwz r1,0(r1)
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lwz r0,4(r1)
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mtlr r0
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blr
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_GLOBAL(call_handle_irq)
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mflr r0
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stw r0,4(r1)
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mtctr r6
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stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
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mr r1,r5
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bctrl
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lwz r1,0(r1)
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lwz r0,4(r1)
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mtlr r0
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blr
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#endif /* CONFIG_IRQSTACKS */
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/*
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* This returns the high 64 bits of the product of two 64-bit numbers.
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*/
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_GLOBAL(mulhdu)
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cmpwi r6,0
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cmpwi cr1,r3,0
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mr r10,r4
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mulhwu r4,r4,r5
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beq 1f
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mulhwu r0,r10,r6
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mullw r7,r10,r5
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addc r7,r0,r7
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addze r4,r4
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1: beqlr cr1 /* all done if high part of A is 0 */
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mr r10,r3
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mullw r9,r3,r5
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mulhwu r3,r3,r5
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beq 2f
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mullw r0,r10,r6
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mulhwu r8,r10,r6
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addc r7,r0,r7
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adde r4,r4,r8
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addze r3,r3
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2: addc r4,r4,r9
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addze r3,r3
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blr
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/*
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* sub_reloc_offset(x) returns x - reloc_offset().
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*/
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_GLOBAL(sub_reloc_offset)
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mflr r0
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bl 1f
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1: mflr r5
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r5,r4,r5
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subf r3,r5,r3
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mtlr r0
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blr
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/*
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* reloc_got2 runs through the .got2 section adding an offset
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* to each entry.
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*/
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_GLOBAL(reloc_got2)
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mflr r11
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lis r7,__got2_start@ha
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addi r7,r7,__got2_start@l
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lis r8,__got2_end@ha
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addi r8,r8,__got2_end@l
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subf r8,r7,r8
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srwi. r8,r8,2
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beqlr
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mtctr r8
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bl 1f
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1: mflr r0
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r0,r4,r0
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add r7,r0,r7
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2: lwz r0,0(r7)
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add r0,r0,r3
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stw r0,0(r7)
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addi r7,r7,4
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bdnz 2b
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mtlr r11
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blr
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/*
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* call_setup_cpu - call the setup_cpu function for this cpu
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* r3 = data offset, r24 = cpu number
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*
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* Setup function is called with:
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* r3 = data offset
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* r4 = ptr to CPU spec (relocated)
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*/
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_GLOBAL(call_setup_cpu)
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addis r4,r3,cur_cpu_spec@ha
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addi r4,r4,cur_cpu_spec@l
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lwz r4,0(r4)
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add r4,r4,r3
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lwz r5,CPU_SPEC_SETUP(r4)
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cmpwi 0,r5,0
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add r5,r5,r3
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beqlr
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mtctr r5
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bctr
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#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
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/* This gets called by via-pmu.c to switch the PLL selection
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* on 750fx CPU. This function should really be moved to some
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* other place (as most of the cpufreq code in via-pmu
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*/
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_GLOBAL(low_choose_750fx_pll)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* If switching to PLL1, disable HID0:BTIC */
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cmplwi cr0,r3,0
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beq 1f
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mfspr r5,SPRN_HID0
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rlwinm r5,r5,0,27,25
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
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rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
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rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
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or r4,r4,r5
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mtspr SPRN_HID1,r4
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/* Store new HID1 image */
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rlwinm r6,r1,0,0,(31-THREAD_SHIFT)
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lwz r6,TI_CPU(r6)
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slwi r6,r6,2
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addis r6,r6,nap_save_hid1@ha
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stw r4,nap_save_hid1@l(r6)
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/* If switching to PLL0, enable HID0:BTIC */
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cmplwi cr0,r3,0
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bne 1f
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mfspr r5,SPRN_HID0
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ori r5,r5,HID0_BTIC
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Return */
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mtmsr r7
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blr
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_GLOBAL(low_choose_7447a_dfs)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1
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insrwi r4,r3,1,9 /* insert parameter into bit 9 */
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sync
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mtspr SPRN_HID1,r4
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sync
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isync
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/* Return */
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mtmsr r7
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blr
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#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
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/*
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* complement mask on the msr then "or" some values on.
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* _nmask_and_or_msr(nmask, value_to_or)
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*/
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_GLOBAL(_nmask_and_or_msr)
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mfmsr r0 /* Get current msr */
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andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
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or r0,r0,r4 /* Or on the bits in r4 (second parm) */
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SYNC /* Some chip revs have problems here... */
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mtmsr r0 /* Update machine state */
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isync
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blr /* Done */
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#ifdef CONFIG_40x
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/*
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* Do an IO access in real mode
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*/
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_GLOBAL(real_readb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsr r0
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sync
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isync
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lbz r3,0(r3)
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sync
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mtmsr r7
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sync
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isync
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blr
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/*
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* Do an IO access in real mode
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*/
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_GLOBAL(real_writeb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsr r0
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sync
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isync
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stb r3,0(r4)
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sync
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mtmsr r7
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sync
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isync
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blr
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#endif /* CONFIG_40x */
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/*
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* Flush instruction cache.
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* This is a no-op on the 601.
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*/
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_GLOBAL(flush_instruction_cache)
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#if defined(CONFIG_8xx)
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isync
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lis r5, IDC_INVALL@h
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mtspr SPRN_IC_CST, r5
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#elif defined(CONFIG_4xx)
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#ifdef CONFIG_403GCX
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li r3, 512
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mtctr r3
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lis r4, KERNELBASE@h
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1: iccci 0, r4
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addi r4, r4, 16
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bdnz 1b
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#else
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lis r3, KERNELBASE@h
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iccci 0,r3
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#endif
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#elif CONFIG_FSL_BOOKE
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BEGIN_FTR_SECTION
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mfspr r3,SPRN_L1CSR0
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ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
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/* msync; isync recommended here */
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mtspr SPRN_L1CSR0,r3
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isync
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blr
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END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
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mfspr r3,SPRN_L1CSR1
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ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
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mtspr SPRN_L1CSR1,r3
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#else
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mfspr r3,SPRN_PVR
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rlwinm r3,r3,16,16,31
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cmpwi 0,r3,1
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beqlr /* for 601, do nothing */
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/* 603/604 processor - use invalidate-all bit in HID0 */
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mfspr r3,SPRN_HID0
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ori r3,r3,HID0_ICFI
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mtspr SPRN_HID0,r3
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#endif /* CONFIG_8xx/4xx */
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isync
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blr
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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* This is a no-op on the 601.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*/
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_KPROBE(__flush_icache_range)
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BEGIN_FTR_SECTION
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blr /* for 601, do nothing */
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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#ifndef CONFIG_44x
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 2b
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#else
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/* Flash invalidate on 44x because we are passed kmapped addresses and
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this doesn't work for userspace pages due to the virtually tagged
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icache. Sigh. */
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iccci 0, r0
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#endif
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sync /* additional sync needed on g4 */
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isync
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blr
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/*
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* Write any modified data cache blocks out to memory.
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* Does not invalidate the corresponding cache lines (especially for
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* any corresponding instruction cache).
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*
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* clean_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(clean_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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blr
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/*
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* Write any modified data cache blocks out to memory and invalidate them.
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* Does not invalidate the corresponding instruction cache blocks.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbf 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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blr
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/*
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* Like above, but invalidate the D-cache. This is used by the 8xx
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* to invalidate the cache so the PPC core doesn't get stale data
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* from the CPM (no cache snooping here :-).
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*
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* invalidate_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(invalidate_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbi 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbi's to get to ram */
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blr
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/*
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* Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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* This is a no-op on the 601 which has a unified cache.
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*
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* void __flush_dcache_icache(void *page)
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*/
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_GLOBAL(__flush_dcache_icache)
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BEGIN_FTR_SECTION
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blr
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
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li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
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mtctr r4
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mr r6,r3
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0: dcbst 0,r3 /* Write line to ram */
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addi r3,r3,L1_CACHE_BYTES
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bdnz 0b
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sync
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#ifdef CONFIG_44x
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/* We don't flush the icache on 44x. Those have a virtual icache
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* and we don't have access to the virtual address here (it's
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* not the page vaddr but where it's mapped in user space). The
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* flushing of the icache on these is handled elsewhere, when
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* a change in the address space occurs, before returning to
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* user space
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*/
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BEGIN_MMU_FTR_SECTION
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blr
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
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#endif /* CONFIG_44x */
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mtctr r4
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1: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 1b
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sync
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isync
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blr
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|
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#ifndef CONFIG_BOOKE
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/*
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* Flush a particular page from the data cache to RAM, identified
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* by its physical address. We turn off the MMU so we can just use
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* the physical address (this may be a highmem page without a kernel
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* mapping).
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*
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* void __flush_dcache_icache_phys(unsigned long physaddr)
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*/
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_GLOBAL(__flush_dcache_icache_phys)
|
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BEGIN_FTR_SECTION
|
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blr /* for 601, do nothing */
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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mfmsr r10
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rlwinm r0,r10,0,28,26 /* clear DR */
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mtmsr r0
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isync
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rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
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li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
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mtctr r4
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mr r6,r3
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0: dcbst 0,r3 /* Write line to ram */
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addi r3,r3,L1_CACHE_BYTES
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bdnz 0b
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sync
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mtctr r4
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1: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 1b
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sync
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mtmsr r10 /* restore DR */
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isync
|
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blr
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#endif /* CONFIG_BOOKE */
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|
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/*
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* Clear pages using the dcbz instruction, which doesn't cause any
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* memory traffic (except to write out any cache lines which get
|
|
* displaced). This only works on cacheable memory.
|
|
*
|
|
* void clear_pages(void *page, int order) ;
|
|
*/
|
|
_GLOBAL(clear_pages)
|
|
li r0,PAGE_SIZE/L1_CACHE_BYTES
|
|
slw r0,r0,r4
|
|
mtctr r0
|
|
1: dcbz 0,r3
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
blr
|
|
|
|
/*
|
|
* Copy a whole page. We use the dcbz instruction on the destination
|
|
* to reduce memory traffic (it eliminates the unnecessary reads of
|
|
* the destination into cache). This requires that the destination
|
|
* is cacheable.
|
|
*/
|
|
#define COPY_16_BYTES \
|
|
lwz r6,4(r4); \
|
|
lwz r7,8(r4); \
|
|
lwz r8,12(r4); \
|
|
lwzu r9,16(r4); \
|
|
stw r6,4(r3); \
|
|
stw r7,8(r3); \
|
|
stw r8,12(r3); \
|
|
stwu r9,16(r3)
|
|
|
|
_GLOBAL(copy_page)
|
|
addi r3,r3,-4
|
|
addi r4,r4,-4
|
|
|
|
li r5,4
|
|
|
|
#if MAX_COPY_PREFETCH > 1
|
|
li r0,MAX_COPY_PREFETCH
|
|
li r11,4
|
|
mtctr r0
|
|
11: dcbt r11,r4
|
|
addi r11,r11,L1_CACHE_BYTES
|
|
bdnz 11b
|
|
#else /* MAX_COPY_PREFETCH == 1 */
|
|
dcbt r5,r4
|
|
li r11,L1_CACHE_BYTES+4
|
|
#endif /* MAX_COPY_PREFETCH */
|
|
li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
|
|
crclr 4*cr0+eq
|
|
2:
|
|
mtctr r0
|
|
1:
|
|
dcbt r11,r4
|
|
dcbz r5,r3
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 32
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 64
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 128
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
#endif
|
|
#endif
|
|
#endif
|
|
bdnz 1b
|
|
beqlr
|
|
crnot 4*cr0+eq,4*cr0+eq
|
|
li r0,MAX_COPY_PREFETCH
|
|
li r11,4
|
|
b 2b
|
|
|
|
/*
|
|
* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
|
|
* void atomic_set_mask(atomic_t mask, atomic_t *addr);
|
|
*/
|
|
_GLOBAL(atomic_clear_mask)
|
|
10: lwarx r5,0,r4
|
|
andc r5,r5,r3
|
|
PPC405_ERR77(0,r4)
|
|
stwcx. r5,0,r4
|
|
bne- 10b
|
|
blr
|
|
_GLOBAL(atomic_set_mask)
|
|
10: lwarx r5,0,r4
|
|
or r5,r5,r3
|
|
PPC405_ERR77(0,r4)
|
|
stwcx. r5,0,r4
|
|
bne- 10b
|
|
blr
|
|
|
|
/*
|
|
* Extended precision shifts.
|
|
*
|
|
* Updated to be valid for shift counts from 0 to 63 inclusive.
|
|
* -- Gabriel
|
|
*
|
|
* R3/R4 has 64 bit value
|
|
* R5 has shift count
|
|
* result in R3/R4
|
|
*
|
|
* ashrdi3: arithmetic right shift (sign propagation)
|
|
* lshrdi3: logical right shift
|
|
* ashldi3: left shift
|
|
*/
|
|
_GLOBAL(__ashrdi3)
|
|
subfic r6,r5,32
|
|
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
|
rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
|
|
sraw r7,r3,r7 # t2 = MSW >> (count-32)
|
|
or r4,r4,r6 # LSW |= t1
|
|
slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
|
|
sraw r3,r3,r5 # MSW = MSW >> count
|
|
or r4,r4,r7 # LSW |= t2
|
|
blr
|
|
|
|
_GLOBAL(__ashldi3)
|
|
subfic r6,r5,32
|
|
slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
|
|
slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
|
|
or r3,r3,r6 # MSW |= t1
|
|
slw r4,r4,r5 # LSW = LSW << count
|
|
or r3,r3,r7 # MSW |= t2
|
|
blr
|
|
|
|
_GLOBAL(__lshrdi3)
|
|
subfic r6,r5,32
|
|
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
|
srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
|
|
or r4,r4,r6 # LSW |= t1
|
|
srw r3,r3,r5 # MSW = MSW >> count
|
|
or r4,r4,r7 # LSW |= t2
|
|
blr
|
|
|
|
/*
|
|
* 64-bit comparison: __ucmpdi2(u64 a, u64 b)
|
|
* Returns 0 if a < b, 1 if a == b, 2 if a > b.
|
|
*/
|
|
_GLOBAL(__ucmpdi2)
|
|
cmplw r3,r5
|
|
li r3,1
|
|
bne 1f
|
|
cmplw r4,r6
|
|
beqlr
|
|
1: li r3,0
|
|
bltlr
|
|
li r3,2
|
|
blr
|
|
|
|
_GLOBAL(abs)
|
|
srawi r4,r3,31
|
|
xor r3,r3,r4
|
|
sub r3,r3,r4
|
|
blr
|
|
|
|
/*
|
|
* Create a kernel thread
|
|
* kernel_thread(fn, arg, flags)
|
|
*/
|
|
_GLOBAL(kernel_thread)
|
|
stwu r1,-16(r1)
|
|
stw r30,8(r1)
|
|
stw r31,12(r1)
|
|
mr r30,r3 /* function */
|
|
mr r31,r4 /* argument */
|
|
ori r3,r5,CLONE_VM /* flags */
|
|
oris r3,r3,CLONE_UNTRACED>>16
|
|
li r4,0 /* new sp (unused) */
|
|
li r0,__NR_clone
|
|
sc
|
|
bns+ 1f /* did system call indicate error? */
|
|
neg r3,r3 /* if so, make return code negative */
|
|
1: cmpwi 0,r3,0 /* parent or child? */
|
|
bne 2f /* return if parent */
|
|
li r0,0 /* make top-level stack frame */
|
|
stwu r0,-16(r1)
|
|
mtlr r30 /* fn addr in lr */
|
|
mr r3,r31 /* load arg and call fn */
|
|
PPC440EP_ERR42
|
|
blrl
|
|
li r0,__NR_exit /* exit if function returns */
|
|
li r3,0
|
|
sc
|
|
2: lwz r30,8(r1)
|
|
lwz r31,12(r1)
|
|
addi r1,r1,16
|
|
blr
|
|
|
|
/*
|
|
* This routine is just here to keep GCC happy - sigh...
|
|
*/
|
|
_GLOBAL(__main)
|
|
blr
|
|
|
|
#ifdef CONFIG_KEXEC
|
|
/*
|
|
* Must be relocatable PIC code callable as a C function.
|
|
*/
|
|
.globl relocate_new_kernel
|
|
relocate_new_kernel:
|
|
/* r3 = page_list */
|
|
/* r4 = reboot_code_buffer */
|
|
/* r5 = start_address */
|
|
|
|
#ifdef CONFIG_FSL_BOOKE
|
|
|
|
mr r29, r3
|
|
mr r30, r4
|
|
mr r31, r5
|
|
|
|
#define ENTRY_MAPPING_KEXEC_SETUP
|
|
#include "fsl_booke_entry_mapping.S"
|
|
#undef ENTRY_MAPPING_KEXEC_SETUP
|
|
|
|
mr r3, r29
|
|
mr r4, r30
|
|
mr r5, r31
|
|
|
|
li r0, 0
|
|
#else
|
|
li r0, 0
|
|
|
|
/*
|
|
* Set Machine Status Register to a known status,
|
|
* switch the MMU off and jump to 1: in a single step.
|
|
*/
|
|
|
|
mr r8, r0
|
|
ori r8, r8, MSR_RI|MSR_ME
|
|
mtspr SPRN_SRR1, r8
|
|
addi r8, r4, 1f - relocate_new_kernel
|
|
mtspr SPRN_SRR0, r8
|
|
sync
|
|
rfi
|
|
|
|
1:
|
|
#endif
|
|
/* from this point address translation is turned off */
|
|
/* and interrupts are disabled */
|
|
|
|
/* set a new stack at the bottom of our page... */
|
|
/* (not really needed now) */
|
|
addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
|
|
stw r0, 0(r1)
|
|
|
|
/* Do the copies */
|
|
li r6, 0 /* checksum */
|
|
mr r0, r3
|
|
b 1f
|
|
|
|
0: /* top, read another word for the indirection page */
|
|
lwzu r0, 4(r3)
|
|
|
|
1:
|
|
/* is it a destination page? (r8) */
|
|
rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
|
|
beq 2f
|
|
|
|
rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
|
|
b 0b
|
|
|
|
2: /* is it an indirection page? (r3) */
|
|
rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
|
|
beq 2f
|
|
|
|
rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
|
|
subi r3, r3, 4
|
|
b 0b
|
|
|
|
2: /* are we done? */
|
|
rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
|
|
beq 2f
|
|
b 3f
|
|
|
|
2: /* is it a source page? (r9) */
|
|
rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
|
|
beq 0b
|
|
|
|
rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
|
|
|
|
li r7, PAGE_SIZE / 4
|
|
mtctr r7
|
|
subi r9, r9, 4
|
|
subi r8, r8, 4
|
|
9:
|
|
lwzu r0, 4(r9) /* do the copy */
|
|
xor r6, r6, r0
|
|
stwu r0, 4(r8)
|
|
dcbst 0, r8
|
|
sync
|
|
icbi 0, r8
|
|
bdnz 9b
|
|
|
|
addi r9, r9, 4
|
|
addi r8, r8, 4
|
|
b 0b
|
|
|
|
3:
|
|
|
|
/* To be certain of avoiding problems with self-modifying code
|
|
* execute a serializing instruction here.
|
|
*/
|
|
isync
|
|
sync
|
|
|
|
/* jump to the entry point, usually the setup routine */
|
|
mtlr r5
|
|
blrl
|
|
|
|
1: b 1b
|
|
|
|
relocate_new_kernel_end:
|
|
|
|
.globl relocate_new_kernel_size
|
|
relocate_new_kernel_size:
|
|
.long relocate_new_kernel_end - relocate_new_kernel
|
|
#endif
|