James Liao b3be457e58 clk: mediatek: Fix PLL registers setting flow ... Write postdiv and pcw settings at the same time for PLLs if postdiv and pcw settings are on the same register. This is need by PLLs such as MT8173 MMPLL and ARM*PLL. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2015-07-28 11:58:52 -07:00
..
clk-gate.c	clk: mediatek: Initialize clk_init_data	2015-05-19 18:40:48 -07:00
clk-gate.h
clk-mt8135.c	clk: mediatek: Fix apmixedsys clock registration	2015-06-04 14:07:07 -07:00
clk-mt8173.c	clk: mediatek: mt8173: Fix enabling of critical clocks	2015-07-06 15:54:13 -07:00
clk-mtk.c
clk-mtk.h	clk: mediatek: Add reset controller support	2015-05-05 22:50:33 -07:00
clk-pll.c	clk: mediatek: Fix PLL registers setting flow	2015-07-28 11:58:52 -07:00
Makefile	clk: mediatek: Add basic clocks for Mediatek MT8173.	2015-05-05 22:50:38 -07:00
reset.c	clk: mediatek: Add reset controller support	2015-05-05 22:50:33 -07:00