b36ba30c8a
Reset controllers and clock controllers are combined into one IP block on Qualcomm chipsets. Usually a reset signal is associated with each clock branch but sometimes a reset signal is associated with a handful of clocks. Either way the register interface is the same; set a bit to assert a reset and clear a bit to deassert a reset. Add support for these types of resets signals. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
6 lines
136 B
Plaintext
6 lines
136 B
Plaintext
config COMMON_CLK_QCOM
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tristate "Support for Qualcomm's clock controllers"
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depends on OF
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select REGMAP_MMIO
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select RESET_CONTROLLER
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