forked from Minki/linux
4c8979b226
And sort them to prevent this from happening again. Reported-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
385 lines
8.1 KiB
C
385 lines
8.1 KiB
C
/*
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* I2C bus driver for Conexant Digicolor SoCs
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*
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* Author: Baruch Siach <baruch@tkos.co.il>
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*
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* Copyright (C) 2015 Paradox Innovation Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#define DEFAULT_FREQ 100000
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#define TIMEOUT_MS 100
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#define II_CONTROL 0x0
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#define II_CONTROL_LOCAL_RESET BIT(0)
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#define II_CLOCKTIME 0x1
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#define II_COMMAND 0x2
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#define II_CMD_START 1
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#define II_CMD_RESTART 2
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#define II_CMD_SEND_ACK 3
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#define II_CMD_GET_ACK 6
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#define II_CMD_GET_NOACK 7
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#define II_CMD_STOP 10
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#define II_COMMAND_GO BIT(7)
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#define II_COMMAND_COMPLETION_STATUS(r) (((r) >> 5) & 3)
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#define II_CMD_STATUS_NORMAL 0
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#define II_CMD_STATUS_ACK_GOOD 1
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#define II_CMD_STATUS_ACK_BAD 2
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#define II_CMD_STATUS_ABORT 3
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#define II_DATA 0x3
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#define II_INTFLAG_CLEAR 0x8
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#define II_INTENABLE 0xa
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struct dc_i2c {
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struct i2c_adapter adap;
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struct device *dev;
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void __iomem *regs;
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struct clk *clk;
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unsigned int frequency;
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struct i2c_msg *msg;
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unsigned int msgbuf_ptr;
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int last;
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spinlock_t lock;
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struct completion done;
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int state;
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int error;
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};
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enum {
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STATE_IDLE,
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STATE_START,
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STATE_ADDR,
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STATE_WRITE,
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STATE_READ,
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STATE_STOP,
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};
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static void dc_i2c_cmd(struct dc_i2c *i2c, u8 cmd)
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{
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writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND);
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}
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static u8 dc_i2c_addr_cmd(struct i2c_msg *msg)
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{
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u8 addr = (msg->addr & 0x7f) << 1;
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if (msg->flags & I2C_M_RD)
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addr |= 1;
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return addr;
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}
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static void dc_i2c_data(struct dc_i2c *i2c, u8 data)
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{
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writeb_relaxed(data, i2c->regs + II_DATA);
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}
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static void dc_i2c_write_byte(struct dc_i2c *i2c, u8 byte)
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{
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dc_i2c_data(i2c, byte);
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dc_i2c_cmd(i2c, II_CMD_SEND_ACK);
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}
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static void dc_i2c_write_buf(struct dc_i2c *i2c)
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{
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dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]);
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}
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static void dc_i2c_next_read(struct dc_i2c *i2c)
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{
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bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len);
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dc_i2c_cmd(i2c, last ? II_CMD_GET_NOACK : II_CMD_GET_ACK);
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}
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static void dc_i2c_stop(struct dc_i2c *i2c)
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{
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i2c->state = STATE_STOP;
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if (i2c->last)
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dc_i2c_cmd(i2c, II_CMD_STOP);
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else
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complete(&i2c->done);
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}
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static u8 dc_i2c_read_byte(struct dc_i2c *i2c)
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{
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return readb_relaxed(i2c->regs + II_DATA);
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}
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static void dc_i2c_read_buf(struct dc_i2c *i2c)
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{
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i2c->msg->buf[i2c->msgbuf_ptr++] = dc_i2c_read_byte(i2c);
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dc_i2c_next_read(i2c);
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}
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static void dc_i2c_set_irq(struct dc_i2c *i2c, int enable)
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{
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if (enable)
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writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR);
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writeb_relaxed(!!enable, i2c->regs + II_INTENABLE);
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}
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static int dc_i2c_cmd_status(struct dc_i2c *i2c)
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{
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u8 cmd = readb_relaxed(i2c->regs + II_COMMAND);
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return II_COMMAND_COMPLETION_STATUS(cmd);
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}
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static void dc_i2c_start_msg(struct dc_i2c *i2c, int first)
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{
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struct i2c_msg *msg = i2c->msg;
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if (!(msg->flags & I2C_M_NOSTART)) {
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i2c->state = STATE_START;
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dc_i2c_cmd(i2c, first ? II_CMD_START : II_CMD_RESTART);
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} else if (msg->flags & I2C_M_RD) {
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i2c->state = STATE_READ;
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dc_i2c_next_read(i2c);
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} else {
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i2c->state = STATE_WRITE;
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dc_i2c_write_buf(i2c);
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}
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}
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static irqreturn_t dc_i2c_irq(int irq, void *dev_id)
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{
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struct dc_i2c *i2c = dev_id;
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int cmd_status = dc_i2c_cmd_status(i2c);
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unsigned long flags;
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u8 addr_cmd;
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writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR);
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spin_lock_irqsave(&i2c->lock, flags);
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if (cmd_status == II_CMD_STATUS_ACK_BAD
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|| cmd_status == II_CMD_STATUS_ABORT) {
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i2c->error = -EIO;
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complete(&i2c->done);
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goto out;
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}
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switch (i2c->state) {
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case STATE_START:
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addr_cmd = dc_i2c_addr_cmd(i2c->msg);
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dc_i2c_write_byte(i2c, addr_cmd);
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i2c->state = STATE_ADDR;
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break;
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case STATE_ADDR:
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if (i2c->msg->flags & I2C_M_RD) {
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dc_i2c_next_read(i2c);
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i2c->state = STATE_READ;
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break;
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}
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i2c->state = STATE_WRITE;
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/* fall through */
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case STATE_WRITE:
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if (i2c->msgbuf_ptr < i2c->msg->len)
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dc_i2c_write_buf(i2c);
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else
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dc_i2c_stop(i2c);
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break;
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case STATE_READ:
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if (i2c->msgbuf_ptr < i2c->msg->len)
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dc_i2c_read_buf(i2c);
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else
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dc_i2c_stop(i2c);
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break;
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case STATE_STOP:
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i2c->state = STATE_IDLE;
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complete(&i2c->done);
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break;
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}
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out:
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spin_unlock_irqrestore(&i2c->lock, flags);
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return IRQ_HANDLED;
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}
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static int dc_i2c_xfer_msg(struct dc_i2c *i2c, struct i2c_msg *msg, int first,
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int last)
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{
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unsigned long timeout = msecs_to_jiffies(TIMEOUT_MS);
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unsigned long flags;
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spin_lock_irqsave(&i2c->lock, flags);
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i2c->msg = msg;
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i2c->msgbuf_ptr = 0;
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i2c->last = last;
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i2c->error = 0;
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reinit_completion(&i2c->done);
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dc_i2c_set_irq(i2c, 1);
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dc_i2c_start_msg(i2c, first);
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spin_unlock_irqrestore(&i2c->lock, flags);
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timeout = wait_for_completion_timeout(&i2c->done, timeout);
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dc_i2c_set_irq(i2c, 0);
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if (timeout == 0) {
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i2c->state = STATE_IDLE;
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return -ETIMEDOUT;
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}
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if (i2c->error)
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return i2c->error;
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return 0;
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}
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static int dc_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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{
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struct dc_i2c *i2c = adap->algo_data;
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int i, ret;
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for (i = 0; i < num; i++) {
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ret = dc_i2c_xfer_msg(i2c, &msgs[i], i == 0, i == num - 1);
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if (ret)
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return ret;
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}
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return num;
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}
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static int dc_i2c_init_hw(struct dc_i2c *i2c)
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{
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unsigned long clk_rate = clk_get_rate(i2c->clk);
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unsigned int clocktime;
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writeb_relaxed(II_CONTROL_LOCAL_RESET, i2c->regs + II_CONTROL);
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udelay(100);
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writeb_relaxed(0, i2c->regs + II_CONTROL);
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udelay(100);
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clocktime = DIV_ROUND_UP(clk_rate, 64 * i2c->frequency);
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if (clocktime < 1 || clocktime > 0xff) {
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dev_err(i2c->dev, "can't set bus speed of %u Hz\n",
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i2c->frequency);
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return -EINVAL;
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}
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writeb_relaxed(clocktime - 1, i2c->regs + II_CLOCKTIME);
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return 0;
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}
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static u32 dc_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
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}
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static const struct i2c_algorithm dc_i2c_algorithm = {
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.master_xfer = dc_i2c_xfer,
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.functionality = dc_i2c_func,
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};
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static int dc_i2c_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct dc_i2c *i2c;
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struct resource *r;
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int ret = 0, irq;
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i2c = devm_kzalloc(&pdev->dev, sizeof(struct dc_i2c), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
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&i2c->frequency))
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i2c->frequency = DEFAULT_FREQ;
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i2c->dev = &pdev->dev;
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platform_set_drvdata(pdev, i2c);
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spin_lock_init(&i2c->lock);
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init_completion(&i2c->done);
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i2c->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(i2c->clk))
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return PTR_ERR(i2c->clk);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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i2c->regs = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(i2c->regs))
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return PTR_ERR(i2c->regs);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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ret = devm_request_irq(&pdev->dev, irq, dc_i2c_irq, 0,
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dev_name(&pdev->dev), i2c);
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if (ret < 0)
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return ret;
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strlcpy(i2c->adap.name, "Conexant Digicolor I2C adapter",
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sizeof(i2c->adap.name));
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i2c->adap.owner = THIS_MODULE;
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i2c->adap.algo = &dc_i2c_algorithm;
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i2c->adap.dev.parent = &pdev->dev;
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i2c->adap.dev.of_node = np;
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i2c->adap.algo_data = i2c;
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ret = dc_i2c_init_hw(i2c);
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if (ret)
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return ret;
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ret = clk_prepare_enable(i2c->clk);
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if (ret < 0)
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return ret;
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ret = i2c_add_adapter(&i2c->adap);
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if (ret < 0) {
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clk_unprepare(i2c->clk);
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return ret;
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}
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return 0;
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}
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static int dc_i2c_remove(struct platform_device *pdev)
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{
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struct dc_i2c *i2c = platform_get_drvdata(pdev);
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i2c_del_adapter(&i2c->adap);
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clk_disable_unprepare(i2c->clk);
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return 0;
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}
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static const struct of_device_id dc_i2c_match[] = {
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{ .compatible = "cnxt,cx92755-i2c" },
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{ },
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};
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static struct platform_driver dc_i2c_driver = {
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.probe = dc_i2c_probe,
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.remove = dc_i2c_remove,
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.driver = {
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.name = "digicolor-i2c",
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.of_match_table = dc_i2c_match,
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},
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};
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module_platform_driver(dc_i2c_driver);
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MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
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MODULE_DESCRIPTION("Conexant Digicolor I2C master driver");
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MODULE_LICENSE("GPL v2");
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