b2edcfc814
Loongson-3 CPU family:
Code-name Brand-name PRId
Loongson-3A R1 Loongson-3A1000 0x6305
Loongson-3A R2 Loongson-3A2000 0x6308
Loongson-3B R1 Loongson-3B1000 0x6306
Loongson-3B R2 Loongson-3B1500 0x6307
Features of R2 revision of Loongson-3A:
- Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache).
- I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is
64 bytes.
- 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way
set-associative).
- Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/
Execute-Inhibit.
[ralf@linux-mips.org: Resolved merge conflicts.]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12751/
Patchwork: https://patchwork.linux-mips.org/patch/13136/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
55 lines
1.2 KiB
C
55 lines
1.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005 Embedded Alley Solutions, Inc
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2009 Jiajie Chen (chenjiajie@cse.buaa.edu.cn)
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* Copyright (C) 2012 Huacai Chen (chenhc@lemote.com)
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*/
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#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
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#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
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/*
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* Override macros used in arch/mips/kernel/head.S.
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*/
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.macro kernel_entry_setup
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#ifdef CONFIG_CPU_LOONGSON3
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.set push
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.set mips64
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/* Set LPA on LOONGSON3 config3 */
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mfc0 t0, $16, 3
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or t0, (0x1 << 7)
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mtc0 t0, $16, 3
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/* Set ELPA on LOONGSON3 pagegrain */
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mfc0 t0, $5, 1
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or t0, (0x1 << 29)
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mtc0 t0, $5, 1
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_ehb
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.set pop
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#endif
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.endm
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/*
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* Do SMP slave processor setup.
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*/
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.macro smp_slave_setup
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#ifdef CONFIG_CPU_LOONGSON3
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.set push
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.set mips64
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/* Set LPA on LOONGSON3 config3 */
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mfc0 t0, $16, 3
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or t0, (0x1 << 7)
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mtc0 t0, $16, 3
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/* Set ELPA on LOONGSON3 pagegrain */
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mfc0 t0, $5, 1
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or t0, (0x1 << 29)
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mtc0 t0, $5, 1
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_ehb
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.set pop
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#endif
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.endm
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#endif /* __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H */
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