forked from Minki/linux
ab64920c37
- Armada 370/XP suspend/resume support - mvebu SoC driver suspend/resume support - irqchip - clocksource - mbus - clk -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJUe0lIAAoJEP45WPkGe8Zn/IgP/jOO8c7t7dohRbAe3axzIcaC DLL7d7j0AScZGXLx1/xJrFFY/P3gn3dlLR7HnT0t4K7vcW0kP4orMGo6FcGicSOZ VzQf88cOkunKf9NTM1Y0LOXVWTHGuACiXAnxook5A6k+l0xQ1t+uewgEKrg/33VK 6WQ6woe2eYFwghkFwL3ybjttOPM5nxPef6v3TZ3LfwSUBsnSm70F1XiO8xZJH+LM fL83P409LGWgohwSaXYRdPJcNM0U7QMNo6i/If9NNBhIkdKb6llhQ/DvI+aXUvqB aD9/4t+Q75yki0mXIin6irltjspWsR8OFbaKZOM5IBFp/XrsKvNU+wy++7z9se9z qfG1QYmKk3ddI0isoksuIJpfbrlbQqFKCGlNkn8HVi4xCYCijNgb5bUrHQ27Aa4U GGisAOhqs9Ktpz96WeNKjvNQBSJZ3ESd6tlLrwCei8DwEdT0Z73jr1aEnulurpPG A3kiUhVpRIU+w0cth5Kix2bZj7JGsykzu1x5xORLE+MN8RSgmoveGyY5CBp2MHrl NxR/u98SD9I/rWT3DwQIKxM5ZqF4AAnyj4SaSWR/f40kWMU+A+eMEfo8VUeO88fl ygeeHTghSf58gbdgganRfDyY8OaQHeYNNKbWK6c7vxyMX98vwHOtOb5JS3nn0p7q Fugy/6qf+ZqYHT4nczJO =uX+e -----END PGP SIGNATURE----- Merge tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu into next/soc Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper: - Armada 370/XP suspend/resume support - mvebu SoC driver suspend/resume support - irqchip - clocksource - mbus - clk * tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu: ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller Signed-off-by: Arnd Bergmann <arnd@arndb.de>
186 lines
4.6 KiB
C
186 lines
4.6 KiB
C
/*
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* Symmetric Multi Processing (SMP) support for Armada XP
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
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* This file implements the routines for preparing the SMP infrastructure
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* and waking up the secondary CPUs
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/mbus.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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#include "armada-370-xp.h"
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#include "pmsu.h"
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#include "coherency.h"
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#define ARMADA_XP_MAX_CPUS 4
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#define AXP_BOOTROM_BASE 0xfff00000
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#define AXP_BOOTROM_SIZE 0x100000
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static struct clk *get_cpu_clk(int cpu)
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{
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struct clk *cpu_clk;
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struct device_node *np = of_get_cpu_node(cpu, NULL);
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if (WARN(!np, "missing cpu node\n"))
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return NULL;
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cpu_clk = of_clk_get(np, 0);
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if (WARN_ON(IS_ERR(cpu_clk)))
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return NULL;
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return cpu_clk;
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}
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static void set_secondary_cpu_clock(unsigned int cpu)
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{
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int thiscpu;
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unsigned long rate;
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struct clk *cpu_clk;
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thiscpu = get_cpu();
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cpu_clk = get_cpu_clk(thiscpu);
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if (!cpu_clk)
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goto out;
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clk_prepare_enable(cpu_clk);
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rate = clk_get_rate(cpu_clk);
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cpu_clk = get_cpu_clk(cpu);
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if (!cpu_clk)
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goto out;
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clk_set_rate(cpu_clk, rate);
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clk_prepare_enable(cpu_clk);
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out:
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put_cpu();
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}
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static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int ret, hw_cpu;
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pr_info("Booting CPU %d\n", cpu);
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hw_cpu = cpu_logical_map(cpu);
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set_secondary_cpu_clock(hw_cpu);
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mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
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/*
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* This is needed to wake up CPUs in the offline state after
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* using CPU hotplug.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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/*
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* This is needed to take secondary CPUs out of reset on the
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* initial boot.
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*/
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ret = mvebu_cpu_reset_deassert(hw_cpu);
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if (ret) {
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pr_warn("unable to boot CPU: %d\n", ret);
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return ret;
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}
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return 0;
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}
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/*
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* When a CPU is brought back online, either through CPU hotplug, or
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* because of the boot of a kexec'ed kernel, the PMSU configuration
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* for this CPU might be in the deep idle state, preventing this CPU
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* from receiving interrupts. Here, we therefore take out the current
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* CPU from this state, which was entered by armada_xp_cpu_die()
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* below.
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*/
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static void armada_xp_secondary_init(unsigned int cpu)
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{
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mvebu_v7_pmsu_idle_exit();
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}
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static void __init armada_xp_smp_init_cpus(void)
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{
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unsigned int ncores = num_possible_cpus();
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if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
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panic("Invalid number of CPUs in DT\n");
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}
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static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *node;
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struct resource res;
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int err;
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flush_cache_all();
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set_cpu_coherent();
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/*
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* In order to boot the secondary CPUs we need to ensure
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* the bootROM is mapped at the correct address.
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*/
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node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
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if (!node)
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panic("Cannot find 'marvell,bootrom' compatible node");
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err = of_address_to_resource(node, 0, &res);
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if (err < 0)
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panic("Cannot get 'bootrom' node address");
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if (res.start != AXP_BOOTROM_BASE ||
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resource_size(&res) != AXP_BOOTROM_SIZE)
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panic("The address for the BootROM is incorrect");
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static void armada_xp_cpu_die(unsigned int cpu)
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{
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/*
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* CPU hotplug is implemented by putting offline CPUs into the
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* deep idle sleep state.
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*/
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armada_370_xp_pmsu_idle_enter(true);
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}
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/*
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* We need a dummy function, so that platform_can_cpu_hotplug() knows
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* we support CPU hotplug. However, the function does not need to do
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* anything, because CPUs going offline can enter the deep idle state
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* by themselves, without any help from a still alive CPU.
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*/
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static int armada_xp_cpu_kill(unsigned int cpu)
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{
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return 1;
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}
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#endif
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struct smp_operations armada_xp_smp_ops __initdata = {
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.smp_init_cpus = armada_xp_smp_init_cpus,
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.smp_prepare_cpus = armada_xp_smp_prepare_cpus,
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.smp_boot_secondary = armada_xp_boot_secondary,
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.smp_secondary_init = armada_xp_secondary_init,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = armada_xp_cpu_die,
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.cpu_kill = armada_xp_cpu_kill,
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#endif
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};
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CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
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&armada_xp_smp_ops);
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