Rex Zhu b02d4081a5 drm/amdgpu: refine cz uvd clock gate logic. ... sw clockgate was used on uvd6.0. when uvd is idle, we gate the uvd clock. when decode, we ungate the uvd clock. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2016-11-23 15:08:39 -05:00
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acp
amdgpu	drm/amdgpu: refine cz uvd clock gate logic.	2016-11-23 15:08:39 -05:00
amdkfd	Linux 4.8-rc8	2016-09-28 12:08:49 +10:00
include	drm/amd/amdgpu: add SI defines/registers	2016-11-11 10:21:08 -05:00
powerplay	drm/amdgpu: refine cz uvd clock gate logic.	2016-11-23 15:08:39 -05:00
scheduler	Linux 4.9-rc4	2016-11-07 09:37:09 +10:00