forked from Minki/linux
b492b8744d
The default monitor that ships with B850v3 requires a 65MHz pixel clock. 65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx, set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous display on both LVDS and HDMI interface. Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
145 lines
3.5 KiB
Plaintext
145 lines
3.5 KiB
Plaintext
/*
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* Copyright 2015 Timesys Corporation.
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* Copyright 2015 General Electric Company
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "imx6q-bx50v3.dtsi"
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/ {
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model = "General Electric B850v3";
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compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
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chosen {
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stdout-path = &uart3;
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};
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};
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&clks {
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assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
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<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
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};
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&ldb {
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fsl,dual-channel;
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status = "okay";
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lvds0: lvds-channel@0 {
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fsl,data-mapping = "spwg";
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fsl,data-width = <24>;
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status = "okay";
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};
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};
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&i2c2 {
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pca9547_ddc: mux@70 {
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compatible = "nxp,pca9547";
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reg = <0x70>;
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#address-cells = <1>;
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#size-cells = <0>;
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mux2_i2c1: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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};
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mux2_i2c2: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1>;
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};
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mux2_i2c3: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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};
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mux2_i2c4: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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};
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mux2_i2c5: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
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};
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mux2_i2c6: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x5>;
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};
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mux2_i2c7: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6>;
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};
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mux2_i2c8: i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7>;
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};
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};
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};
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&hdmi {
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ddc-i2c-bus = <&mux2_i2c1>;
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};
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&mux1_i2c1 {
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ads7830@4a {
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compatible = "ti,ads7830";
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reg = <0x4a>;
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};
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};
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