237 lines
6.4 KiB
C
237 lines
6.4 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv04.h"
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#include <core/gpuobj.h>
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#include <core/option.h>
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#include <subdev/timer.h>
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#define NV44_GART_SIZE (512 * 1024 * 1024)
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#define NV44_GART_PAGE ( 4 * 1024)
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/*******************************************************************************
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* VM map/unmap callbacks
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******************************************************************************/
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static void
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nv44_vm_fill(struct nvkm_memory *pgt, dma_addr_t null,
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dma_addr_t *list, u32 pte, u32 cnt)
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{
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u32 base = (pte << 2) & ~0x0000000f;
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u32 tmp[4];
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tmp[0] = nvkm_ro32(pgt, base + 0x0);
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tmp[1] = nvkm_ro32(pgt, base + 0x4);
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tmp[2] = nvkm_ro32(pgt, base + 0x8);
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tmp[3] = nvkm_ro32(pgt, base + 0xc);
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while (cnt--) {
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u32 addr = list ? (*list++ >> 12) : (null >> 12);
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switch (pte++ & 0x3) {
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case 0:
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tmp[0] &= ~0x07ffffff;
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tmp[0] |= addr;
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break;
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case 1:
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tmp[0] &= ~0xf8000000;
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tmp[0] |= addr << 27;
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tmp[1] &= ~0x003fffff;
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tmp[1] |= addr >> 5;
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break;
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case 2:
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tmp[1] &= ~0xffc00000;
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tmp[1] |= addr << 22;
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tmp[2] &= ~0x0001ffff;
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tmp[2] |= addr >> 10;
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break;
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case 3:
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tmp[2] &= ~0xfffe0000;
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tmp[2] |= addr << 17;
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tmp[3] &= ~0x00000fff;
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tmp[3] |= addr >> 15;
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break;
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}
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}
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nvkm_wo32(pgt, base + 0x0, tmp[0]);
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nvkm_wo32(pgt, base + 0x4, tmp[1]);
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nvkm_wo32(pgt, base + 0x8, tmp[2]);
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nvkm_wo32(pgt, base + 0xc, tmp[3] | 0x40000000);
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}
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static void
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nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_memory *pgt,
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struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
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{
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struct nv04_mmu *mmu = nv04_mmu(vma->vm->mmu);
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u32 tmp[4];
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int i;
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nvkm_kmap(pgt);
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if (pte & 3) {
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u32 max = 4 - (pte & 3);
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u32 part = (cnt > max) ? max : cnt;
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nv44_vm_fill(pgt, mmu->null, list, pte, part);
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pte += part;
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list += part;
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cnt -= part;
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}
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while (cnt >= 4) {
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for (i = 0; i < 4; i++)
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tmp[i] = *list++ >> 12;
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nvkm_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27);
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nvkm_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22);
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nvkm_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17);
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nvkm_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000);
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cnt -= 4;
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}
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if (cnt)
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nv44_vm_fill(pgt, mmu->null, list, pte, cnt);
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nvkm_done(pgt);
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}
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static void
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nv44_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
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{
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struct nv04_mmu *mmu = nv04_mmu(vma->vm->mmu);
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nvkm_kmap(pgt);
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if (pte & 3) {
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u32 max = 4 - (pte & 3);
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u32 part = (cnt > max) ? max : cnt;
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nv44_vm_fill(pgt, mmu->null, NULL, pte, part);
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pte += part;
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cnt -= part;
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}
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while (cnt >= 4) {
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nvkm_wo32(pgt, pte++ * 4, 0x00000000);
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nvkm_wo32(pgt, pte++ * 4, 0x00000000);
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nvkm_wo32(pgt, pte++ * 4, 0x00000000);
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nvkm_wo32(pgt, pte++ * 4, 0x00000000);
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cnt -= 4;
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}
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if (cnt)
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nv44_vm_fill(pgt, mmu->null, NULL, pte, cnt);
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nvkm_done(pgt);
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}
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static void
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nv44_vm_flush(struct nvkm_vm *vm)
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{
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struct nv04_mmu *mmu = nv04_mmu(vm->mmu);
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struct nvkm_device *device = mmu->base.subdev.device;
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nvkm_wr32(device, 0x100814, mmu->base.limit - NV44_GART_PAGE);
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nvkm_wr32(device, 0x100808, 0x00000020);
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nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x100808) & 0x00000001)
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break;
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);
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nvkm_wr32(device, 0x100808, 0x00000000);
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}
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/*******************************************************************************
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* MMU subdev
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******************************************************************************/
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static int
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nv44_mmu_oneinit(struct nvkm_mmu *base)
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{
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struct nv04_mmu *mmu = nv04_mmu(base);
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struct nvkm_device *device = mmu->base.subdev.device;
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int ret;
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mmu->nullp = dma_alloc_coherent(device->dev, 16 * 1024,
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&mmu->null, GFP_KERNEL);
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if (!mmu->nullp) {
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nvkm_warn(&mmu->base.subdev, "unable to allocate dummy pages\n");
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mmu->null = 0;
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}
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ret = nvkm_vm_create(&mmu->base, 0, NV44_GART_SIZE, 0, 4096, NULL,
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&mmu->vm);
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if (ret)
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return ret;
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
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(NV44_GART_SIZE / NV44_GART_PAGE) * 4,
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512 * 1024, true,
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&mmu->vm->pgt[0].mem[0]);
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mmu->vm->pgt[0].refcount[0] = 1;
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return ret;
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}
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static void
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nv44_mmu_init(struct nvkm_mmu *base)
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{
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struct nv04_mmu *mmu = nv04_mmu(base);
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struct nvkm_device *device = mmu->base.subdev.device;
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struct nvkm_memory *gart = mmu->vm->pgt[0].mem[0];
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u32 addr;
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/* calculate vram address of this PRAMIN block, object must be
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* allocated on 512KiB alignment, and not exceed a total size
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* of 512KiB for this to work correctly
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*/
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addr = nvkm_rd32(device, 0x10020c);
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addr -= ((nvkm_memory_addr(gart) >> 19) + 1) << 19;
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nvkm_wr32(device, 0x100850, 0x80000000);
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nvkm_wr32(device, 0x100818, mmu->null);
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nvkm_wr32(device, 0x100804, NV44_GART_SIZE);
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nvkm_wr32(device, 0x100850, 0x00008000);
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nvkm_mask(device, 0x10008c, 0x00000200, 0x00000200);
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nvkm_wr32(device, 0x100820, 0x00000000);
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nvkm_wr32(device, 0x10082c, 0x00000001);
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nvkm_wr32(device, 0x100800, addr | 0x00000010);
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}
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static const struct nvkm_mmu_func
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nv44_mmu = {
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.dtor = nv04_mmu_dtor,
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.oneinit = nv44_mmu_oneinit,
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.init = nv44_mmu_init,
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.limit = NV44_GART_SIZE,
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.dma_bits = 39,
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.pgt_bits = 32 - 12,
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.spg_shift = 12,
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.lpg_shift = 12,
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.map_sg = nv44_vm_map_sg,
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.unmap = nv44_vm_unmap,
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.flush = nv44_vm_flush,
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};
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int
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nv44_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
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{
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if (device->type == NVKM_DEVICE_AGP ||
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!nvkm_boolopt(device->cfgopt, "NvPCIE", true))
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return nv04_mmu_new(device, index, pmmu);
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return nv04_mmu_new_(&nv44_mmu, device, index, pmmu);
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}
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