forked from Minki/linux
08344f3b43
This is a collection of a few late fixes and other misc. stuff that had dependencies on things being merged from other trees. The Renesas R-Car power domain handling, and the Nvidia Tegra USB support both hand notable changes that required changing the DT binding in a way that only provides compatibility with old DT blobs on new kernels but not vice versa. As a consequence, the DT changes are based on top of the driver changes and are now in this branch. For NXP i.MX and Samsung Exynos, the changes in here depend on other changes that got merged through the clk maintainer tree. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAV0Sse2CrR//JCVInAQJoOg//VQwAUxayKGfYVzhJjhHdYbVA9kWYczHb wizFbF51XPylQzfGgHxEZJgdO3y2Ks54J7xaCK7oSUPEBT0rHsLQunHhq0aVQpew 1c06vEysYMkRclG7C0zN7i4gwdig+L4r6kUguTvb+nyJS3RISg0LaSoANVU65dQ5 +g4DLRrX1QlZPBXR8Fc/S1gTFXU+dO1S0oJFnK9ZZTgmsGg4GA0qC60hdsv+WeSv uzS4FJoxSy9MzoAFqmnWIa4jBV9I1Rg5vi7dfoBbTW1XOAMpq+GVLLU+Lvso0Jqw xWjBSmPl6l/cZ7BhpzWq8knKOsEezh5LLrVRXViVCGfTIFdlObxyHzeKcJp25V1p mL98MBXobn9Rly9hJxyzpeNWITZ6qJYR+IQy3Lsuk5KrdZG2f4uTErtoqmYRI3Pn vuXoi13NUeoCrHZJZ+fNUGwx5a5/hgUQXP5u+98uucQSqIVxe0cGnQVnFm84X81r Sj/dXxFlFBZfqfE8rf1cFd+YEbKtpF13vEURAQWrnEzBmJSTu7Cp8qdA5hX5CeK4 DW9bsu5hkWwnzoC2Ox/ZQVms4aI3q8s2xuu28GEJJdCE2IUiSnag/5vhGBzd4dTm 9R69RhE9y4EOhw+0z1O0LfoKoo6YyUQa+OUNVIwEfFjcCdZiMQIdZWi2PLv4jeAR jBBbpcWtHLo= =I0Be -----END PGP SIGNATURE----- Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "This is a collection of a few late fixes and other misc stuff that had dependencies on things being merged from other trees. The Renesas R-Car power domain handling, and the Nvidia Tegra USB support both hand notable changes that required changing the DT binding in a way that only provides compatibility with old DT blobs on new kernels but not vice versa. As a consequence, the DT changes are based on top of the driver changes and are now in this branch. For NXP i.MX and Samsung Exynos, the changes in here depend on other changes that got merged through the clk maintainer tree" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (35 commits) ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3 ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250 ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk ARM: dts: exynos: Add DMC bus node for Exynos3250 ARM: tegra: Enable XUSB on Nyan ARM: tegra: Enable XUSB on Jetson TK1 ARM: tegra: Enable XUSB on Venice2 ARM: tegra: Add Tegra124 XUSB controller ARM: tegra: Move Tegra124 to the new XUSB pad controller binding ARM: dts: r8a7794: Use SYSC "always-on" PM Domain ARM: dts: r8a7793: Use SYSC "always-on" PM Domain ...
599 lines
16 KiB
Plaintext
599 lines
16 KiB
Plaintext
/*
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* Device Tree Source for Renesas r8a7779
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Simon Horman
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7779-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/r8a7779-sysc.h>
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/ {
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compatible = "renesas,r8a7779";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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clock-frequency = <1000000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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clock-frequency = <1000000000>;
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power-domains = <&sysc R8A7779_PD_ARM1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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clock-frequency = <1000000000>;
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power-domains = <&sysc R8A7779_PD_ARM2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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clock-frequency = <1000000000>;
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power-domains = <&sysc R8A7779_PD_ARM3>;
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};
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};
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aliases {
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spi0 = &hspi0;
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spi1 = &hspi1;
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spi2 = &hspi2;
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};
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gic: interrupt-controller@f0001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xf0001000 0x1000>,
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<0xf0000100 0x100>;
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};
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timer@f0000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xf0000600 0x20>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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clocks = <&cpg_clocks R8A7779_CLK_ZS>;
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};
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gpio0: gpio@ffc40000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc40000 0x2c>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio1: gpio@ffc41000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc41000 0x2c>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio2: gpio@ffc42000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc42000 0x2c>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio3: gpio@ffc43000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc43000 0x2c>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio4: gpio@ffc44000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc44000 0x2c>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio5: gpio@ffc45000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc45000 0x2c>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio6: gpio@ffc46000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc46000 0x2c>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 9>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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irqpin0: interrupt-controller@fe78001c {
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compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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status = "disabled";
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interrupt-controller;
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reg = <0xfe78001c 4>,
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<0xfe780010 4>,
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<0xfe780024 4>,
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<0xfe780044 4>,
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<0xfe780064 4>,
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<0xfe780000 4>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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sense-bitfield-width = <2>;
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};
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i2c0: i2c@ffc70000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc70000 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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i2c1: i2c@ffc71000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc71000 0x1000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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i2c2: i2c@ffc72000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc72000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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i2c3: i2c@ffc73000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc73000 0x1000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scif0: serial@ffe40000 {
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compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
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"renesas,scif";
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reg = <0xffe40000 0x100>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scif1: serial@ffe41000 {
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compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
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"renesas,scif";
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reg = <0xffe41000 0x100>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scif2: serial@ffe42000 {
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compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
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"renesas,scif";
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reg = <0xffe42000 0x100>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scif3: serial@ffe43000 {
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compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
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"renesas,scif";
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reg = <0xffe43000 0x100>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scif4: serial@ffe44000 {
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compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
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"renesas,scif";
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reg = <0xffe44000 0x100>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scif5: serial@ffe45000 {
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compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
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"renesas,scif";
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reg = <0xffe45000 0x100>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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pfc: pfc@fffc0000 {
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compatible = "renesas,pfc-r8a7779";
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reg = <0xfffc0000 0x23c>;
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};
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thermal@ffc48000 {
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compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
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reg = <0xffc48000 0x38>;
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};
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tmu0: timer@ffd80000 {
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compatible = "renesas,tmu-r8a7779", "renesas,tmu";
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reg = <0xffd80000 0x30>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
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clock-names = "fck";
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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#renesas,channels = <3>;
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status = "disabled";
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};
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tmu1: timer@ffd81000 {
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compatible = "renesas,tmu-r8a7779", "renesas,tmu";
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reg = <0xffd81000 0x30>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
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clock-names = "fck";
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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#renesas,channels = <3>;
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status = "disabled";
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};
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tmu2: timer@ffd82000 {
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compatible = "renesas,tmu-r8a7779", "renesas,tmu";
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reg = <0xffd82000 0x30>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
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clock-names = "fck";
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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#renesas,channels = <3>;
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status = "disabled";
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};
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sata: sata@fc600000 {
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compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
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reg = <0xfc600000 0x2000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7779_CLK_SATA>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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};
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sdhi0: sd@ffe4c000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4c000 0x100>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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sdhi1: sd@ffe4d000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4d000 0x100>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
|
|
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi2: sd@ffe4e000 {
|
|
compatible = "renesas,sdhi-r8a7779";
|
|
reg = <0xffe4e000 0x100>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
|
|
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi3: sd@ffe4f000 {
|
|
compatible = "renesas,sdhi-r8a7779";
|
|
reg = <0xffe4f000 0x100>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
|
|
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hspi0: spi@fffc7000 {
|
|
compatible = "renesas,hspi-r8a7779", "renesas,hspi";
|
|
reg = <0xfffc7000 0x18>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
|
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hspi1: spi@fffc8000 {
|
|
compatible = "renesas,hspi-r8a7779", "renesas,hspi";
|
|
reg = <0xfffc8000 0x18>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
|
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hspi2: spi@fffc6000 {
|
|
compatible = "renesas,hspi-r8a7779", "renesas,hspi";
|
|
reg = <0xfffc6000 0x18>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
|
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
du: display@fff80000 {
|
|
compatible = "renesas,du-r8a7779";
|
|
reg = <0 0xfff80000 0 0x40000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp1_clks R8A7779_CLK_DU>;
|
|
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
du_out_rgb0: endpoint {
|
|
};
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_rgb1: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
/* External root clock */
|
|
extal_clk: extal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overriden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/* External SCIF clock */
|
|
scif_clk: scif {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/* Special CPG clocks */
|
|
cpg_clocks: clocks@ffc80000 {
|
|
compatible = "renesas,r8a7779-cpg-clocks";
|
|
reg = <0xffc80000 0x30>;
|
|
clocks = <&extal_clk>;
|
|
#clock-cells = <1>;
|
|
clock-output-names = "plla", "z", "zs", "s",
|
|
"s1", "p", "b", "out";
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
/* Fixed factor clocks */
|
|
i_clk: i {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
};
|
|
s3_clk: s3 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
};
|
|
s4_clk: s4 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
|
#clock-cells = <0>;
|
|
clock-div = <16>;
|
|
clock-mult = <1>;
|
|
};
|
|
g_clk: g {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
|
#clock-cells = <0>;
|
|
clock-div = <24>;
|
|
clock-mult = <1>;
|
|
};
|
|
|
|
/* Gate clocks */
|
|
mstp0_clks: clocks@ffc80030 {
|
|
compatible = "renesas,r8a7779-mstp-clocks",
|
|
"renesas,cpg-mstp-clocks";
|
|
reg = <0xffc80030 4>;
|
|
clocks = <&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7779_CLK_HSPI R8A7779_CLK_TMU2
|
|
R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
|
|
R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
|
|
R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
|
|
R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
|
|
R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
|
|
R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
|
|
R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
|
|
>;
|
|
clock-output-names =
|
|
"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
|
|
"hscif0", "scif5", "scif4", "scif3", "scif2",
|
|
"scif1", "scif0", "i2c3", "i2c2", "i2c1",
|
|
"i2c0";
|
|
};
|
|
mstp1_clks: clocks@ffc80034 {
|
|
compatible = "renesas,r8a7779-mstp-clocks",
|
|
"renesas,cpg-mstp-clocks";
|
|
reg = <0xffc80034 4>, <0xffc80044 4>;
|
|
clocks = <&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_S>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7779_CLK_USB01 R8A7779_CLK_USB2
|
|
R8A7779_CLK_DU R8A7779_CLK_VIN2
|
|
R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
|
|
R8A7779_CLK_ETHER R8A7779_CLK_SATA
|
|
R8A7779_CLK_PCIE R8A7779_CLK_VIN3
|
|
>;
|
|
clock-output-names =
|
|
"usb01", "usb2",
|
|
"du", "vin2",
|
|
"vin1", "vin0",
|
|
"ether", "sata",
|
|
"pcie", "vin3";
|
|
};
|
|
mstp3_clks: clocks@ffc8003c {
|
|
compatible = "renesas,r8a7779-mstp-clocks",
|
|
"renesas,cpg-mstp-clocks";
|
|
reg = <0xffc8003c 4>;
|
|
clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
|
|
<&s4_clk>, <&s4_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
|
|
R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
|
|
R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
|
|
>;
|
|
clock-output-names =
|
|
"sdhi3", "sdhi2", "sdhi1", "sdhi0",
|
|
"mmc1", "mmc0";
|
|
};
|
|
};
|
|
|
|
sysc: system-controller@ffd85000 {
|
|
compatible = "renesas,r8a7779-sysc";
|
|
reg = <0xffd85000 0x0200>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
};
|