Paul Burton ad68f8d3c2 MIPS: JZ4740: define IRQ numbers based on number of intc IRQs ... For interrupts numbered after those of the interrupt controller, define their numbers based upon the number of interrupts provided by the SoC interrupt controller. This is in preparation for supporting newer Ingenic SoCs which provide more interrupts. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10143/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2015-06-21 21:53:04 +02:00
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asm	MIPS: JZ4740: define IRQ numbers based on number of intc IRQs	2015-06-21 21:53:04 +02:00
uapi/asm	MIPS: KVM: Expose MSA registers	2015-03-27 21:25:21 +00:00