ad3bba06b6
S3AN flashes use a specific opcode to read the status register. We currently use the SPI_S3AN flag to decide whether this specific SR read opcode should be used, but SPI_S3AN is about to disappear, so let's add a new flag. Note that we use the same bit as SPI_S3AN implies SPI_NOR_XSR_RDY and vice versa. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> |
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| .. | ||
| aspeed-smc.c | ||
| cadence-quadspi.c | ||
| hisi-sfc.c | ||
| intel-spi-pci.c | ||
| intel-spi-platform.c | ||
| intel-spi.c | ||
| intel-spi.h | ||
| Kconfig | ||
| Makefile | ||
| mtk-quadspi.c | ||
| nxp-spifi.c | ||
| spi-nor.c | ||