ab3f02fc23
Since we assume set_mb() to result in a single store followed by a full memory barrier, employ WRITE_ONCE(). Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
61 lines
1.6 KiB
C
61 lines
1.6 KiB
C
#ifndef _ASM_UM_BARRIER_H_
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#define _ASM_UM_BARRIER_H_
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#include <asm/asm.h>
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#include <asm/segment.h>
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#include <asm/cpufeature.h>
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#include <asm/cmpxchg.h>
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#include <asm/nops.h>
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#include <linux/kernel.h>
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#include <linux/irqflags.h>
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_X86_32
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#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
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#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
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#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
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#else /* CONFIG_X86_32 */
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#define mb() asm volatile("mfence" : : : "memory")
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#define rmb() asm volatile("lfence" : : : "memory")
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#define wmb() asm volatile("sfence" : : : "memory")
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#endif /* CONFIG_X86_32 */
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#ifdef CONFIG_X86_PPRO_FENCE
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#define dma_rmb() rmb()
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#else /* CONFIG_X86_PPRO_FENCE */
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#define dma_rmb() barrier()
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#endif /* CONFIG_X86_PPRO_FENCE */
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#define dma_wmb() barrier()
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define set_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
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#define read_barrier_depends() do { } while (0)
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#define smp_read_barrier_depends() do { } while (0)
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/*
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* Stop RDTSC speculation. This is needed when you need to use RDTSC
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* (or get_cycles or vread that possibly accesses the TSC) in a defined
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* code region.
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*
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* (Could use an alternative three way for this if there was one.)
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*/
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static inline void rdtsc_barrier(void)
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{
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alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC,
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"lfence", X86_FEATURE_LFENCE_RDTSC);
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}
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#endif
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