forked from Minki/linux
57fbcce37b
This enum is already perfectly aliased to enum nl80211_band, and the only reason for it is that we get IEEE80211_NUM_BANDS out of it. There's no really good reason to not declare the number of bands in nl80211 though, so do that and remove the cfg80211 one. Signed-off-by: Johannes Berg <johannes.berg@intel.com>
654 lines
15 KiB
C
654 lines
15 KiB
C
/*
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Broadcom B43 wireless driver
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Common PHY routines
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Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
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Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
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Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
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Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
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Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
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Boston, MA 02110-1301, USA.
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*/
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#include "phy_common.h"
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#include "phy_g.h"
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#include "phy_a.h"
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#include "phy_n.h"
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#include "phy_lp.h"
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#include "phy_ht.h"
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#include "phy_lcn.h"
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#include "phy_ac.h"
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#include "b43.h"
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#include "main.h"
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int b43_phy_allocate(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &(dev->phy);
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int err;
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phy->ops = NULL;
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switch (phy->type) {
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case B43_PHYTYPE_G:
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#ifdef CONFIG_B43_PHY_G
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phy->ops = &b43_phyops_g;
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#endif
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break;
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case B43_PHYTYPE_N:
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#ifdef CONFIG_B43_PHY_N
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phy->ops = &b43_phyops_n;
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#endif
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break;
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case B43_PHYTYPE_LP:
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#ifdef CONFIG_B43_PHY_LP
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phy->ops = &b43_phyops_lp;
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#endif
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break;
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case B43_PHYTYPE_HT:
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#ifdef CONFIG_B43_PHY_HT
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phy->ops = &b43_phyops_ht;
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#endif
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break;
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case B43_PHYTYPE_LCN:
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#ifdef CONFIG_B43_PHY_LCN
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phy->ops = &b43_phyops_lcn;
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#endif
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break;
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case B43_PHYTYPE_AC:
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#ifdef CONFIG_B43_PHY_AC
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phy->ops = &b43_phyops_ac;
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#endif
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break;
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}
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if (B43_WARN_ON(!phy->ops))
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return -ENODEV;
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err = phy->ops->allocate(dev);
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if (err)
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phy->ops = NULL;
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return err;
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}
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void b43_phy_free(struct b43_wldev *dev)
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{
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dev->phy.ops->free(dev);
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dev->phy.ops = NULL;
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}
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int b43_phy_init(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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const struct b43_phy_operations *ops = phy->ops;
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int err;
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/* During PHY init we need to use some channel. On the first init this
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* function is called *before* b43_op_config, so our pointer is NULL.
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*/
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if (!phy->chandef) {
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phy->chandef = &dev->wl->hw->conf.chandef;
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phy->channel = phy->chandef->chan->hw_value;
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}
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phy->ops->switch_analog(dev, true);
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b43_software_rfkill(dev, false);
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err = ops->init(dev);
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if (err) {
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b43err(dev->wl, "PHY init failed\n");
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goto err_block_rf;
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}
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phy->do_full_init = false;
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err = b43_switch_channel(dev, phy->channel);
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if (err) {
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b43err(dev->wl, "PHY init: Channel switch to default failed\n");
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goto err_phy_exit;
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}
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return 0;
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err_phy_exit:
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phy->do_full_init = true;
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if (ops->exit)
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ops->exit(dev);
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err_block_rf:
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b43_software_rfkill(dev, true);
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return err;
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}
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void b43_phy_exit(struct b43_wldev *dev)
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{
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const struct b43_phy_operations *ops = dev->phy.ops;
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b43_software_rfkill(dev, true);
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dev->phy.do_full_init = true;
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if (ops->exit)
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ops->exit(dev);
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}
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bool b43_has_hardware_pctl(struct b43_wldev *dev)
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{
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if (!dev->phy.hardware_power_control)
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return false;
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if (!dev->phy.ops->supports_hwpctl)
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return false;
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return dev->phy.ops->supports_hwpctl(dev);
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}
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void b43_radio_lock(struct b43_wldev *dev)
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{
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u32 macctl;
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#if B43_DEBUG
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B43_WARN_ON(dev->phy.radio_locked);
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dev->phy.radio_locked = true;
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#endif
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macctl = b43_read32(dev, B43_MMIO_MACCTL);
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macctl |= B43_MACCTL_RADIOLOCK;
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b43_write32(dev, B43_MMIO_MACCTL, macctl);
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/* Commit the write and wait for the firmware
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* to finish any radio register access. */
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b43_read32(dev, B43_MMIO_MACCTL);
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udelay(10);
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}
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void b43_radio_unlock(struct b43_wldev *dev)
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{
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u32 macctl;
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#if B43_DEBUG
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B43_WARN_ON(!dev->phy.radio_locked);
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dev->phy.radio_locked = false;
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#endif
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/* Commit any write */
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b43_read16(dev, B43_MMIO_PHY_VER);
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/* unlock */
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macctl = b43_read32(dev, B43_MMIO_MACCTL);
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macctl &= ~B43_MACCTL_RADIOLOCK;
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b43_write32(dev, B43_MMIO_MACCTL, macctl);
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}
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void b43_phy_lock(struct b43_wldev *dev)
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{
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#if B43_DEBUG
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B43_WARN_ON(dev->phy.phy_locked);
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dev->phy.phy_locked = true;
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#endif
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B43_WARN_ON(dev->dev->core_rev < 3);
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if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
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b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
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}
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void b43_phy_unlock(struct b43_wldev *dev)
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{
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#if B43_DEBUG
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B43_WARN_ON(!dev->phy.phy_locked);
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dev->phy.phy_locked = false;
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#endif
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B43_WARN_ON(dev->dev->core_rev < 3);
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if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
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b43_power_saving_ctl_bits(dev, 0);
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}
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static inline void assert_mac_suspended(struct b43_wldev *dev)
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{
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if (!B43_DEBUG)
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return;
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if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
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(dev->mac_suspended <= 0)) {
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b43dbg(dev->wl, "PHY/RADIO register access with "
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"enabled MAC.\n");
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dump_stack();
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}
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}
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u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
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{
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assert_mac_suspended(dev);
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dev->phy.writes_counter = 0;
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return dev->phy.ops->radio_read(dev, reg);
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}
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void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
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{
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assert_mac_suspended(dev);
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if (b43_bus_host_is_pci(dev->dev) &&
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++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
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b43_read32(dev, B43_MMIO_MACCTL);
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dev->phy.writes_counter = 1;
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}
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dev->phy.ops->radio_write(dev, reg, value);
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}
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void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
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{
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b43_radio_write16(dev, offset,
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b43_radio_read16(dev, offset) & mask);
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}
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void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
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{
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b43_radio_write16(dev, offset,
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b43_radio_read16(dev, offset) | set);
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}
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void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
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{
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b43_radio_write16(dev, offset,
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(b43_radio_read16(dev, offset) & mask) | set);
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}
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bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
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u16 value, int delay, int timeout)
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{
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u16 val;
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int i;
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for (i = 0; i < timeout; i += delay) {
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val = b43_radio_read(dev, offset);
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if ((val & mask) == value)
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return true;
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udelay(delay);
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}
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return false;
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}
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u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
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{
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assert_mac_suspended(dev);
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dev->phy.writes_counter = 0;
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if (dev->phy.ops->phy_read)
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return dev->phy.ops->phy_read(dev, reg);
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b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
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return b43_read16(dev, B43_MMIO_PHY_DATA);
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}
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void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
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{
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assert_mac_suspended(dev);
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if (b43_bus_host_is_pci(dev->dev) &&
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++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
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b43_read16(dev, B43_MMIO_PHY_VER);
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dev->phy.writes_counter = 1;
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}
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if (dev->phy.ops->phy_write)
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return dev->phy.ops->phy_write(dev, reg, value);
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b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
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b43_write16(dev, B43_MMIO_PHY_DATA, value);
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}
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void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
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{
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b43_phy_write(dev, destreg, b43_phy_read(dev, srcreg));
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}
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void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
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{
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if (dev->phy.ops->phy_maskset) {
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assert_mac_suspended(dev);
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dev->phy.ops->phy_maskset(dev, offset, mask, 0);
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} else {
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b43_phy_write(dev, offset,
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b43_phy_read(dev, offset) & mask);
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}
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}
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void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
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{
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if (dev->phy.ops->phy_maskset) {
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assert_mac_suspended(dev);
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dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
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} else {
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b43_phy_write(dev, offset,
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b43_phy_read(dev, offset) | set);
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}
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}
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void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
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{
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if (dev->phy.ops->phy_maskset) {
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assert_mac_suspended(dev);
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dev->phy.ops->phy_maskset(dev, offset, mask, set);
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} else {
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b43_phy_write(dev, offset,
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(b43_phy_read(dev, offset) & mask) | set);
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}
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}
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void b43_phy_put_into_reset(struct b43_wldev *dev)
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{
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u32 tmp;
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switch (dev->dev->bus_type) {
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#ifdef CONFIG_B43_BCMA
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case B43_BUS_BCMA:
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tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
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tmp &= ~B43_BCMA_IOCTL_GMODE;
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tmp |= B43_BCMA_IOCTL_PHY_RESET;
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tmp |= BCMA_IOCTL_FGC;
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bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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udelay(1);
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tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
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tmp &= ~BCMA_IOCTL_FGC;
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bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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udelay(1);
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break;
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#endif
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#ifdef CONFIG_B43_SSB
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case B43_BUS_SSB:
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tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
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tmp &= ~B43_TMSLOW_GMODE;
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tmp |= B43_TMSLOW_PHYRESET;
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tmp |= SSB_TMSLOW_FGC;
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ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
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usleep_range(1000, 2000);
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tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
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tmp &= ~SSB_TMSLOW_FGC;
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ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
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usleep_range(1000, 2000);
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break;
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#endif
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}
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}
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void b43_phy_take_out_of_reset(struct b43_wldev *dev)
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{
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u32 tmp;
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switch (dev->dev->bus_type) {
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#ifdef CONFIG_B43_BCMA
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case B43_BUS_BCMA:
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/* Unset reset bit (with forcing clock) */
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tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
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tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
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tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
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tmp |= BCMA_IOCTL_FGC;
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bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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udelay(1);
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/* Do not force clock anymore */
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tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
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tmp &= ~BCMA_IOCTL_FGC;
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tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
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bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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udelay(1);
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break;
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#endif
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#ifdef CONFIG_B43_SSB
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case B43_BUS_SSB:
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/* Unset reset bit (with forcing clock) */
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tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
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tmp &= ~B43_TMSLOW_PHYRESET;
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tmp &= ~B43_TMSLOW_PHYCLKEN;
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tmp |= SSB_TMSLOW_FGC;
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ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
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ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
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usleep_range(1000, 2000);
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tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
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tmp &= ~SSB_TMSLOW_FGC;
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tmp |= B43_TMSLOW_PHYCLKEN;
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ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
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ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
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usleep_range(1000, 2000);
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break;
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#endif
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}
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}
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int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
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{
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struct b43_phy *phy = &(dev->phy);
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u16 channelcookie, savedcookie;
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int err;
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/* First we set the channel radio code to prevent the
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* firmware from sending ghost packets.
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*/
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channelcookie = new_channel;
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if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
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channelcookie |= B43_SHM_SH_CHAN_5GHZ;
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/* FIXME: set 40Mhz flag if required */
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if (0)
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channelcookie |= B43_SHM_SH_CHAN_40MHZ;
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savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
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/* Now try to switch the PHY hardware channel. */
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err = phy->ops->switch_channel(dev, new_channel);
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if (err)
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goto err_restore_cookie;
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/* Wait for the radio to tune to the channel and stabilize. */
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msleep(8);
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return 0;
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err_restore_cookie:
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b43_shm_write16(dev, B43_SHM_SHARED,
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B43_SHM_SH_CHAN, savedcookie);
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return err;
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}
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void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
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{
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struct b43_phy *phy = &dev->phy;
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b43_mac_suspend(dev);
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phy->ops->software_rfkill(dev, blocked);
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phy->radio_on = !blocked;
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b43_mac_enable(dev);
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}
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/**
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* b43_phy_txpower_adjust_work - TX power workqueue.
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*
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* Workqueue for updating the TX power parameters in hardware.
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*/
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void b43_phy_txpower_adjust_work(struct work_struct *work)
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{
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struct b43_wl *wl = container_of(work, struct b43_wl,
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txpower_adjust_work);
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struct b43_wldev *dev;
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mutex_lock(&wl->mutex);
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dev = wl->current_dev;
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|
|
if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
|
|
dev->phy.ops->adjust_txpower(dev);
|
|
|
|
mutex_unlock(&wl->mutex);
|
|
}
|
|
|
|
void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
|
|
{
|
|
struct b43_phy *phy = &dev->phy;
|
|
unsigned long now = jiffies;
|
|
enum b43_txpwr_result result;
|
|
|
|
if (!(flags & B43_TXPWR_IGNORE_TIME)) {
|
|
/* Check if it's time for a TXpower check. */
|
|
if (time_before(now, phy->next_txpwr_check_time))
|
|
return; /* Not yet */
|
|
}
|
|
/* The next check will be needed in two seconds, or later. */
|
|
phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
|
|
|
|
if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
|
|
(dev->dev->board_type == SSB_BOARD_BU4306))
|
|
return; /* No software txpower adjustment needed */
|
|
|
|
result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
|
|
if (result == B43_TXPWR_RES_DONE)
|
|
return; /* We are done. */
|
|
B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
|
|
B43_WARN_ON(phy->ops->adjust_txpower == NULL);
|
|
|
|
/* We must adjust the transmission power in hardware.
|
|
* Schedule b43_phy_txpower_adjust_work(). */
|
|
ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
|
|
}
|
|
|
|
int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
|
|
{
|
|
const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
|
|
unsigned int a, b, c, d;
|
|
unsigned int average;
|
|
u32 tmp;
|
|
|
|
tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
|
|
a = tmp & 0xFF;
|
|
b = (tmp >> 8) & 0xFF;
|
|
c = (tmp >> 16) & 0xFF;
|
|
d = (tmp >> 24) & 0xFF;
|
|
if (a == 0 || a == B43_TSSI_MAX ||
|
|
b == 0 || b == B43_TSSI_MAX ||
|
|
c == 0 || c == B43_TSSI_MAX ||
|
|
d == 0 || d == B43_TSSI_MAX)
|
|
return -ENOENT;
|
|
/* The values are OK. Clear them. */
|
|
tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
|
|
(B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
|
|
b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
|
|
|
|
if (is_ofdm) {
|
|
a = (a + 32) & 0x3F;
|
|
b = (b + 32) & 0x3F;
|
|
c = (c + 32) & 0x3F;
|
|
d = (d + 32) & 0x3F;
|
|
}
|
|
|
|
/* Get the average of the values with 0.5 added to each value. */
|
|
average = (a + b + c + d + 2) / 4;
|
|
if (is_ofdm) {
|
|
/* Adjust for CCK-boost */
|
|
if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
|
|
& B43_HF_CCKBOOST)
|
|
average = (average >= 13) ? (average - 13) : 0;
|
|
}
|
|
|
|
return average;
|
|
}
|
|
|
|
void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
|
|
{
|
|
b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
|
|
}
|
|
|
|
|
|
bool b43_is_40mhz(struct b43_wldev *dev)
|
|
{
|
|
return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
|
|
}
|
|
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
|
|
void b43_phy_force_clock(struct b43_wldev *dev, bool force)
|
|
{
|
|
u32 tmp;
|
|
|
|
WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
|
|
dev->phy.type != B43_PHYTYPE_HT &&
|
|
dev->phy.type != B43_PHYTYPE_AC);
|
|
|
|
switch (dev->dev->bus_type) {
|
|
#ifdef CONFIG_B43_BCMA
|
|
case B43_BUS_BCMA:
|
|
tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
|
|
if (force)
|
|
tmp |= BCMA_IOCTL_FGC;
|
|
else
|
|
tmp &= ~BCMA_IOCTL_FGC;
|
|
bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_B43_SSB
|
|
case B43_BUS_SSB:
|
|
tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
|
|
if (force)
|
|
tmp |= SSB_TMSLOW_FGC;
|
|
else
|
|
tmp &= ~SSB_TMSLOW_FGC;
|
|
ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
|
|
break;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
|
|
struct b43_c32 b43_cordic(int theta)
|
|
{
|
|
static const u32 arctg[] = {
|
|
2949120, 1740967, 919879, 466945, 234379, 117304,
|
|
58666, 29335, 14668, 7334, 3667, 1833,
|
|
917, 458, 229, 115, 57, 29,
|
|
};
|
|
u8 i;
|
|
s32 tmp;
|
|
s8 signx = 1;
|
|
u32 angle = 0;
|
|
struct b43_c32 ret = { .i = 39797, .q = 0, };
|
|
|
|
while (theta > (180 << 16))
|
|
theta -= (360 << 16);
|
|
while (theta < -(180 << 16))
|
|
theta += (360 << 16);
|
|
|
|
if (theta > (90 << 16)) {
|
|
theta -= (180 << 16);
|
|
signx = -1;
|
|
} else if (theta < -(90 << 16)) {
|
|
theta += (180 << 16);
|
|
signx = -1;
|
|
}
|
|
|
|
for (i = 0; i <= 17; i++) {
|
|
if (theta > angle) {
|
|
tmp = ret.i - (ret.q >> i);
|
|
ret.q += ret.i >> i;
|
|
ret.i = tmp;
|
|
angle += arctg[i];
|
|
} else {
|
|
tmp = ret.i + (ret.q >> i);
|
|
ret.q -= ret.i >> i;
|
|
ret.i = tmp;
|
|
angle -= arctg[i];
|
|
}
|
|
}
|
|
|
|
ret.i *= signx;
|
|
ret.q *= signx;
|
|
|
|
return ret;
|
|
}
|