a71a468a50
This patch adds support for the DAI BCLK to be generated by multiplying Rate * Channels * Word Size (RCW). This now gives 3 options for BCLK clocking and synchronisation :- 1. BCLK = Rate * x 2. BCLK = MCLK / x 3. BCLK = Rate * Chn * Word Size. (New) Changes:- o Add support for RCW generation of BCLK o Update Documentation to include RCW. o Update DAI documentation for label = value DAI modes. o Add RCW support to wm8731, wm8750 and pxa2xx-i2s drivers. Signed-off-by: Liam Girdwood <lg@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
547 lines
16 KiB
Plaintext
547 lines
16 KiB
Plaintext
ASoC currently supports the three main Digital Audio Interfaces (DAI) found on
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SoC controllers and portable audio CODECS today, namely AC97, I2S and PCM.
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AC97
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====
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AC97 is a five wire interface commonly found on many PC sound cards. It is
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now also popular in many portable devices. This DAI has a reset line and time
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multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines.
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The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
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frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
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frame is 21uS long and is divided into 13 time slots.
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The AC97 specification can be found at :-
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http://www.intel.com/design/chipsets/audio/ac97_r23.pdf
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I2S
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===
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I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
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Rx lines are used for audio transmision, whilst the bit clock (BCLK) and
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left/right clock (LRC) synchronise the link. I2S is flexible in that either the
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controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
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usually varies depending on the sample rate and the master system clock
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(SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
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ADC and DAC LRCLK's, this allows for similtanious capture and playback at
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different sample rates.
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I2S has several different operating modes:-
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o I2S - MSB is transmitted on the falling edge of the first BCLK after LRC
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transition.
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o Left Justified - MSB is transmitted on transition of LRC.
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o Right Justified - MSB is transmitted sample size BCLK's before LRC
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transition.
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PCM
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===
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PCM is another 4 wire interface, very similar to I2S, that can support a more
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flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
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to synchronise the link whilst the Tx and Rx lines are used to transmit and
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receive the audio data. Bit clock usually varies depending on sample rate
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whilst sync runs at the sample rate. PCM also supports Time Division
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Multiplexing (TDM) in that several devices can use the bus similtaniuosly (This
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is sometimes referred to as network mode).
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Common PCM operating modes:-
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o Mode A - MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
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o Mode B - MSB is transmitted on rising edge of FRAME/SYNC.
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ASoC DAI Configuration
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======================
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Every CODEC DAI and SoC DAI must have their capabilities defined in order to
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be configured together at runtime when the audio and clocking parameters are
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known. This is achieved by creating an array of struct snd_soc_hw_mode in the
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the CODEC and SoC interface drivers. Each element in the array describes a DAI
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mode and each mode is usually based upon the DAI system clock to sample rate
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ratio (FS).
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i.e. 48k sample rate @ 256 FS = sytem clock of 12.288 MHz
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48000 * 256 = 12288000
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The CPU and Codec DAI modes are then ANDed together at runtime to determine the
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rutime DAI configuration for both the Codec and CPU.
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When creating a new codec or SoC DAI it's probably best to start of with a few
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sample rates first and then test your interface.
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struct snd_soc_dai_mode is defined (in soc.h) as:-
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/* SoC DAI mode */
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struct snd_soc_dai_mode {
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u16 fmt; /* SND_SOC_DAIFMT_* */
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u16 tdm; /* SND_SOC_HWTDM_* */
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u64 pcmfmt; /* SNDRV_PCM_FMTBIT_* */
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u16 pcmrate; /* SND_SOC_HWRATE_* */
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u16 pcmdir:2; /* SND_SOC_HWDIR_* */
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u16 flags:8; /* hw flags */
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u16 fs; /* mclk to rate divider */
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u64 bfs; /* mclk to bclk dividers */
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unsigned long priv; /* private mode data */
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};
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fmt:
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----
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This field defines the DAI mode hardware format (e.g. I2S settings) and
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supports the following settings:-
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1) hardware DAI formats
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#define SND_SOC_DAIFMT_I2S (1 << 0) /* I2S mode */
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#define SND_SOC_DAIFMT_RIGHT_J (1 << 1) /* Right justified mode */
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#define SND_SOC_DAIFMT_LEFT_J (1 << 2) /* Left Justified mode */
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#define SND_SOC_DAIFMT_DSP_A (1 << 3) /* L data msb after FRM */
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#define SND_SOC_DAIFMT_DSP_B (1 << 4) /* L data msb during FRM */
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#define SND_SOC_DAIFMT_AC97 (1 << 5) /* AC97 */
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2) hw DAI signal inversions
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#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */
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#define SND_SOC_DAIFMT_NB_IF (1 << 9) /* normal bclk + inv frm */
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#define SND_SOC_DAIFMT_IB_NF (1 << 10) /* invert bclk + nor frm */
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#define SND_SOC_DAIFMT_IB_IF (1 << 11) /* invert bclk + frm */
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3) hw clock masters
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This is wrt the codec, the inverse is true for the interface
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i.e. if the codec is clk and frm master then the interface is
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clk and frame slave.
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#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & frm master */
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#define SND_SOC_DAIFMT_CBS_CFM (1 << 13) /* codec clk slave & frm master */
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#define SND_SOC_DAIFMT_CBM_CFS (1 << 14) /* codec clk master & frame slave */
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#define SND_SOC_DAIFMT_CBS_CFS (1 << 15) /* codec clk & frm slave */
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At least one option from each section must be selected. Multiple selections are
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also supported e.g.
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_RIGHT_J | \
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SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_IB_NF | \
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SND_SOC_DAIFMT_IB_IF
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tdm:
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------
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This field defines the Time Division Multiplexing left and right word
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positions for the DAI mode if applicable. Set to SND_SOC_DAITDM_LRDW(0,0) for
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no TDM.
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pcmfmt:
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---------
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The hardware PCM format. This describes the PCM formats supported by the DAI
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mode e.g.
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
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SNDRV_PCM_FORMAT_S24_3LE
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pcmrate:
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----------
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The PCM sample rates supported by the DAI mode. e.g.
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.pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
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SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000
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pcmdir:
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---------
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The stream directions supported by this mode. e.g. playback and capture
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flags:
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--------
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The DAI hardware flags supported by the mode.
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/* use bfs mclk divider mode (BCLK = MCLK / x) */
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#define SND_SOC_DAI_BFS_DIV 0x1
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/* use bfs rate mulitplier (BCLK = RATE * x)*/
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#define SND_SOC_DAI_BFS_RATE 0x2
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/* use bfs rcw multiplier (BCLK = RATE * CHN * WORD SIZE) */
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#define SND_SOC_DAI_BFS_RCW 0x4
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/* capture and playback can use different clocks */
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#define SND_SOC_DAI_ASYNC 0x8
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NOTE: Bitclock division and mulitiplication modes can be safely matched by the
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core logic.
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fs:
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-----
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The FS supported by this DAI mode FS is the ratio between the system clock and
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the sample rate. See above
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bfs:
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------
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BFS is the ratio of BCLK to MCLK or the ratio of BCLK to sample rate (this
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depends on the codec or CPU DAI).
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The BFS supported by the DAI mode. This can either be the ratio between the
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bitclock (BCLK) and the sample rate OR the ratio between the system clock and
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the sample rate. Depends on the flags above.
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priv:
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-----
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private codec mode data.
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Examples
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========
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Note that Codec DAI and CPU DAI examples are interchangeable in these examples
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as long as the bus master is reversed. i.e.
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SND_SOC_DAIFMT_CBM_CFM would become SND_SOC_DAIFMT_CBS_CFS
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and vice versa.
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This applies to all SND_SOC_DAIFMT_CB*_CF*.
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Example 1
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---------
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Simple codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
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BCLK of either MCLK/2 or MCLK/4.
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/* codec master */
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_DIV,
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.fs = 256,
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.bfs = SND_SOC_FSBD(2) | SND_SOC_FSBD(4),
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}
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Example 2
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---------
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Simple codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
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BCLK of either Rate * 32 or Rate * 64.
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/* codec master */
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_RATE,
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.fs = 256,
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.bfs = 32,
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},
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_RATE,
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.fs = 256,
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.bfs = 64,
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},
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Example 3
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---------
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Codec that runs at 8k & 48k @ 256FS in master mode, can generate a BCLK that
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is a multiple of Rate * channels * word size. (RCW) i.e.
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BCLK = 8000 * 2 * 16 (8k, stereo, 16bit)
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= 256kHz
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This codecs supports a RCW multiple of 1,2
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_RCW,
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.fs = 256,
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.bfs = SND_SOC_FSBW(1) | SND_SOC_FSBW(2),
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}
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Example 4
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---------
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Codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
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BCLK of either Rate * 32 or Rate * 64. Codec can also run in slave mode as long
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as BCLK is rate * 32 or rate * 64.
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/* codec master */
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_RATE,
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.fs = 256,
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.bfs = 32,
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},
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_RATE,
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.fs = 256,
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.bfs = 64,
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},
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/* codec slave */
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmdir = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_RATE,
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.fs = SND_SOC_FS_ALL,
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.bfs = 32,
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},
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmdir = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_RATE,
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.fs = SND_SOC_FS_ALL,
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.bfs = 64,
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},
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Example 5
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---------
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Codec that only runs at 8k, 16k, 32k, 48k, 96k @ 128FS, 192FS & 256FS in master
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mode and can generate a BCLK of MCLK / (1,2,4,8,16). Codec can also run in slave
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mode as and does not care about FS or BCLK (as long as there is enough bandwidth).
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#define CODEC_FSB \
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(SND_SOC_FSBD(1) | SND_SOC_FSBD(2) | SND_SOC_FSBD(4) | \
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SND_SOC_FSBD(8) | SND_SOC_FSBD(16))
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#define CODEC_RATES \
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(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |\
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
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/* codec master @ 128, 192 & 256 FS */
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = CODEC_RATES,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_DIV,
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.fs = 128,
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.bfs = CODEC_FSB,
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},
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = CODEC_RATES,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_DIV,
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.fs = 192,
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.bfs = CODEC_FSB
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},
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = CODEC_RATES,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_DIV,
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.fs = 256,
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.bfs = CODEC_FSB,
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},
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/* codec slave */
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = CODEC_RATES,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.fs = SND_SOC_FS_ALL,
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.bfs = SND_SOC_FSB_ALL,
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},
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Example 6
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---------
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Codec that only runs at 8k, 44.1k, 48k @ different FS in master mode (for use
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with a fixed MCLK) and can generate a BCLK of MCLK / (1,2,4,8,16).
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Codec can also run in slave mode as and does not care about FS or BCLK (as long
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as there is enough bandwidth). Codec can support 16, 24 and 32 bit PCM sample
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sizes.
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#define CODEC_FSB \
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(SND_SOC_FSBD(1) | SND_SOC_FSBD(2) | SND_SOC_FSBD(4) | \
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SND_SOC_FSBD(8) | SND_SOC_FSBD(16))
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#define CODEC_PCM_FORMATS \
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(SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
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SNDRV_PCM_FORMAT_S24_3LE | SNDRV_PCM_FORMAT_S24_LE | SNDRV_PCM_FORMAT_S32_LE)
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/* codec master */
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = SNDRV_PCM_RATE_8000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_DIV,
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.fs = 1536,
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.bfs = CODEC_FSB,
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},
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = SNDRV_PCM_RATE_44100,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_DIV,
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.fs = 272,
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.bfs = CODEC_FSB,
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},
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
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.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
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.pcmrate = SNDRV_PCM_RATE_48000,
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.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
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.flags = SND_SOC_DAI_BFS_DIV,
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.fs = 256,
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.bfs = CODEC_FSB,
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},
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/* codec slave */
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{
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.fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
|
|
.pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
|
|
.pcmrate = CODEC_RATES,
|
|
.pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
|
|
.fs = SND_SOC_FS_ALL,
|
|
.bfs = SND_SOC_FSB_ALL,
|
|
},
|
|
|
|
|
|
Example 7
|
|
---------
|
|
AC97 Codec that does not support VRA (i.e only runs at 48k).
|
|
|
|
#define AC97_DIR \
|
|
(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
|
|
|
|
#define AC97_PCM_FORMATS \
|
|
(SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S18_3LE | \
|
|
SNDRV_PCM_FORMAT_S20_3LE)
|
|
|
|
/* AC97 with no VRA */
|
|
{
|
|
.pcmfmt = AC97_PCM_FORMATS,
|
|
.pcmrate = SNDRV_PCM_RATE_48000,
|
|
}
|
|
|
|
|
|
Example 8
|
|
---------
|
|
|
|
CPU DAI that supports 8k - 48k @ 256FS and BCLK = MCLK / 4 in master mode.
|
|
Slave mode (CPU DAI is FRAME master) supports 8k - 96k at any FS as long as
|
|
BCLK = 64 * rate. (Intel XScale I2S controller).
|
|
|
|
#define PXA_I2S_DAIFMT \
|
|
(SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF)
|
|
|
|
#define PXA_I2S_DIR \
|
|
(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
|
|
|
|
#define PXA_I2S_RATES \
|
|
(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
|
|
SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
|
|
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
|
|
|
|
/* priv is divider */
|
|
static struct snd_soc_dai_mode pxa2xx_i2s_modes[] = {
|
|
/* pxa2xx I2S frame and clock master modes */
|
|
{
|
|
.fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
|
|
.pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
|
|
.pcmrate = SNDRV_PCM_RATE_8000,
|
|
.pcmdir = PXA_I2S_DIR,
|
|
.flags = SND_SOC_DAI_BFS_DIV,
|
|
.fs = 256,
|
|
.bfs = SND_SOC_FSBD(4),
|
|
.priv = 0x48,
|
|
},
|
|
{
|
|
.fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
|
|
.pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
|
|
.pcmrate = SNDRV_PCM_RATE_11025,
|
|
.pcmdir = PXA_I2S_DIR,
|
|
.flags = SND_SOC_DAI_BFS_DIV,
|
|
.fs = 256,
|
|
.bfs = SND_SOC_FSBD(4),
|
|
.priv = 0x34,
|
|
},
|
|
{
|
|
.fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
|
|
.pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
|
|
.pcmrate = SNDRV_PCM_RATE_16000,
|
|
.pcmdir = PXA_I2S_DIR,
|
|
.flags = SND_SOC_DAI_BFS_DIV,
|
|
.fs = 256,
|
|
.bfs = SND_SOC_FSBD(4),
|
|
.priv = 0x24,
|
|
},
|
|
{
|
|
.fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
|
|
.pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
|
|
.pcmrate = SNDRV_PCM_RATE_22050,
|
|
.pcmdir = PXA_I2S_DIR,
|
|
.flags = SND_SOC_DAI_BFS_DIV,
|
|
.fs = 256,
|
|
.bfs = SND_SOC_FSBD(4),
|
|
.priv = 0x1a,
|
|
},
|
|
{
|
|
.fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
|
|
.pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
|
|
.pcmrate = SNDRV_PCM_RATE_44100,
|
|
.pcmdir = PXA_I2S_DIR,
|
|
.flags = SND_SOC_DAI_BFS_DIV,
|
|
.fs = 256,
|
|
.bfs = SND_SOC_FSBD(4),
|
|
.priv = 0xd,
|
|
},
|
|
{
|
|
.fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
|
|
.pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
|
|
.pcmrate = SNDRV_PCM_RATE_48000,
|
|
.pcmdir = PXA_I2S_DIR,
|
|
.flags = SND_SOC_DAI_BFS_DIV,
|
|
.fs = 256,
|
|
.bfs = SND_SOC_FSBD(4),
|
|
.priv = 0xc,
|
|
},
|
|
|
|
/* pxa2xx I2S frame master and clock slave mode */
|
|
{
|
|
.fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBM_CFS,
|
|
.pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
|
|
.pcmrate = PXA_I2S_RATES,
|
|
.pcmdir = PXA_I2S_DIR,
|
|
.fs = SND_SOC_FS_ALL,
|
|
.flags = SND_SOC_DAI_BFS_RATE,
|
|
.bfs = 64,
|
|
.priv = 0x48,
|
|
},
|
|
};
|