linux/arch/riscv
Palmer Dabbelt a6de21baf6
RISC-V: Fix some RV32 bugs and build failures
This patch set fixes up various failures in the RV32I port.  The fixes
are all nominally independent, but are really only testable together
because the RV32I port fails to build without all of them.  The patch
set includes:

* The removal of tishift on RV32I targets, as 128-bit integers are not
  supported by the toolchain.
* The removal of swiotlb from RV32I targets, since all physical
  addresses can be mapped by all hardware on all existing RV32I targets.
* The addition of ummodi3 and udivmoddi4 from an old version of GCC that
  was licensed under GPLv2 as generic code, along with their use on
  RV32I targets.
* A fix to our page alignment logic within ioremap for RV32I targets.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-22 17:39:08 -07:00
..
configs irqchip: add a SiFive PLIC driver 2018-08-13 08:31:32 -07:00
include riscv: Add support to no-FPU systems 2018-10-22 17:38:26 -07:00
kernel RISC-V: Fix some RV32 bugs and build failures 2018-10-22 17:39:08 -07:00
lib RISC-V: Build tishift only on 64-bit 2018-10-22 17:02:55 -07:00
mm RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap 2018-10-22 17:02:56 -07:00
Kconfig RISC-V: Fix some RV32 bugs and build failures 2018-10-22 17:39:08 -07:00
Kconfig.debug RISC-V: Cosmetic menuconfig changes 2018-10-22 17:38:20 -07:00
Makefile riscv: Add support to no-FPU systems 2018-10-22 17:38:26 -07:00