81994e0ffc
The s3c2410fb driver is too deeply intertwined with the s3c24xx platform code. Change it in a way that avoids the use of platform header files but having all interface data in a platform_data header, and the private register definitions next to the driver itself. One ugly bit here is that the driver pokes directly into gpio registers, which are owned by another driver. Passing the mapped addresses in platform_data is somewhat suboptimal, but it is a small improvement over the previous version. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200806182059.2431-33-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
144 lines
4.4 KiB
C
144 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*/
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#ifndef ___ASM_ARCH_REGS_LCD_H
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#define ___ASM_ARCH_REGS_LCD_H
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/*
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* a couple of values are used as platform data in
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* include/linux/platform_data/fb-s3c2410.h and not
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* duplicated here.
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*/
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#include <linux/platform_data/fb-s3c2410.h>
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#define S3C2410_LCDREG(x) (x)
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/* LCD control registers */
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#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
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#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04)
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#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08)
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#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C)
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#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10)
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#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
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#define S3C2410_LCDCON1_MMODE (1<<7)
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#define S3C2410_LCDCON1_DSCAN4 (0<<5)
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#define S3C2410_LCDCON1_STN4 (1<<5)
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#define S3C2410_LCDCON1_STN8 (2<<5)
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#define S3C2410_LCDCON1_TFT (3<<5)
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#define S3C2410_LCDCON1_STN1BPP (0<<1)
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#define S3C2410_LCDCON1_STN2GREY (1<<1)
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#define S3C2410_LCDCON1_STN4GREY (2<<1)
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#define S3C2410_LCDCON1_STN8BPP (3<<1)
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#define S3C2410_LCDCON1_STN12BPP (4<<1)
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#define S3C2410_LCDCON1_ENVID (1)
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#define S3C2410_LCDCON1_MODEMASK 0x1E
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#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
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#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
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#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
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#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
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#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
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#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
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#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
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#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
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#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
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#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
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#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
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#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
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#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
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#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
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/* LDCCON4 changes for STN mode on the S3C2412 */
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#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
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#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
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#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
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#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
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/* framebuffer start addressed */
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#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14)
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#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18)
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#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C)
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#define S3C2410_LCDBANK(x) ((x) << 21)
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#define S3C2410_LCDBASEU(x) (x)
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#define S3C2410_OFFSIZE(x) ((x) << 11)
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#define S3C2410_PAGEWIDTH(x) (x)
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/* colour lookup and miscellaneous controls */
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#define S3C2410_REDLUT S3C2410_LCDREG(0x20)
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#define S3C2410_GREENLUT S3C2410_LCDREG(0x24)
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#define S3C2410_BLUELUT S3C2410_LCDREG(0x28)
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#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
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#define S3C2410_TPAL S3C2410_LCDREG(0x50)
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#define S3C2410_TPAL_EN (1<<24)
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/* interrupt info */
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#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
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#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
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#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
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#define S3C2410_LCDINT_FIWSEL (1<<2)
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#define S3C2410_LCDINT_FRSYNC (1<<1)
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#define S3C2410_LCDINT_FICNT (1<<0)
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/* s3c2442 extra stn registers */
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#define S3C2442_REDLUT S3C2410_LCDREG(0x20)
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#define S3C2442_GREENLUT S3C2410_LCDREG(0x24)
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#define S3C2442_BLUELUT S3C2410_LCDREG(0x28)
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#define S3C2442_DITHMODE S3C2410_LCDREG(0x20)
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#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
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#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
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/* S3C2412 registers */
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#define S3C2412_TPAL S3C2410_LCDREG(0x20)
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#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
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#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
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#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
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#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
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#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
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#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
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#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
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#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
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#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
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#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
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#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
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#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
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/* general registers */
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/* base of the LCD registers, where INTPND, INTSRC and then INTMSK
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* are available. */
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#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54)
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#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24)
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#define S3C24XX_LCDINTPND (0x00)
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#define S3C24XX_LCDSRCPND (0x04)
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#define S3C24XX_LCDINTMSK (0x08)
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#endif /* ___ASM_ARCH_REGS_LCD_H */
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