7afa0033d6
[Why] pflip interrupt would not be enabled promptly if a pipe is disabled and re-enabled, causing flip_done timeout error during DP compliance tests [How] Enable pflip interrupt upon pipe enablement Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
787 lines
34 KiB
C
787 lines
34 KiB
C
/* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_MEM_INPUT_DCN10_H__
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#define __DC_MEM_INPUT_DCN10_H__
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#include "hubp.h"
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#define TO_DCN10_HUBP(hubp)\
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container_of(hubp, struct dcn10_hubp, base)
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/* Register address initialization macro for all ASICs (including those with reduced functionality) */
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#define HUBP_REG_LIST_DCN(id)\
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SRI(DCHUBP_CNTL, HUBP, id),\
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SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
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SRI(HUBPREQ_DEBUG, HUBP, id),\
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SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
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SRI(DCSURF_TILING_CONFIG, HUBP, id),\
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SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
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SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
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SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
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SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
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SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
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SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
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SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
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SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
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SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \
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SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \
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SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
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SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
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SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
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SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
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SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
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SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
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SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
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SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
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SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
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SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
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SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
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SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
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SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
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SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
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SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
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SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
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SRI(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),\
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SRI(HUBPRET_CONTROL, HUBPRET, id),\
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SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
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SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
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SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
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SRI(BLANK_OFFSET_0, HUBPREQ, id),\
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SRI(BLANK_OFFSET_1, HUBPREQ, id),\
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SRI(DST_DIMENSIONS, HUBPREQ, id),\
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SRI(DST_AFTER_SCALER, HUBPREQ, id),\
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SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
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SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
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SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
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SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
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SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
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SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
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SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
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SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
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SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
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SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
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SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
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SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
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SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
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SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
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SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
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SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
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SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
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SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
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SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
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SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
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SRI(HUBP_CLK_CNTL, HUBP, id)
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/* Register address initialization macro for ASICs with VM */
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#define HUBP_REG_LIST_DCN_VM(id)\
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SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
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SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
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SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
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SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
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SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
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#define HUBP_REG_LIST_DCN10(id)\
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HUBP_REG_LIST_DCN(id),\
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HUBP_REG_LIST_DCN_VM(id),\
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SRI(PREFETCH_SETTINS, HUBPREQ, id),\
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SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
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SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
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SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
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SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
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SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
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SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
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SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
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SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
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SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
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SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
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SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
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SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
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SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
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SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
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SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
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SRI(CURSOR_SETTINS, HUBPREQ, id), \
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SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
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SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
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SRI(CURSOR_SIZE, CURSOR, id), \
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SRI(CURSOR_CONTROL, CURSOR, id), \
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SRI(CURSOR_POSITION, CURSOR, id), \
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SRI(CURSOR_HOT_SPOT, CURSOR, id), \
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SRI(CURSOR_DST_OFFSET, CURSOR, id)
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#define HUBP_COMMON_REG_VARIABLE_LIST \
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uint32_t DCHUBP_CNTL; \
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uint32_t HUBPREQ_DEBUG_DB; \
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uint32_t HUBPREQ_DEBUG; \
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uint32_t DCSURF_ADDR_CONFIG; \
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uint32_t DCSURF_TILING_CONFIG; \
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uint32_t DCSURF_SURFACE_PITCH; \
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uint32_t DCSURF_SURFACE_PITCH_C; \
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uint32_t DCSURF_SURFACE_CONFIG; \
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uint32_t DCSURF_FLIP_CONTROL; \
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uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \
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uint32_t DCSURF_PRI_VIEWPORT_START; \
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uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \
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uint32_t DCSURF_SEC_VIEWPORT_START; \
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uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \
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uint32_t DCSURF_PRI_VIEWPORT_START_C; \
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uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \
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uint32_t DCSURF_SEC_VIEWPORT_START_C; \
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uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \
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uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \
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uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \
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uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \
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uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \
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uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \
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uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \
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uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \
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uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \
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uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \
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uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C; \
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uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_C; \
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uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \
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uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \
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uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C; \
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uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_C; \
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uint32_t DCSURF_SURFACE_INUSE; \
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uint32_t DCSURF_SURFACE_INUSE_HIGH; \
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uint32_t DCSURF_SURFACE_INUSE_C; \
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uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \
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uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \
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uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \
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uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \
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uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \
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uint32_t DCSURF_SURFACE_CONTROL; \
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uint32_t DCSURF_SURFACE_FLIP_INTERRUPT; \
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uint32_t HUBPRET_CONTROL; \
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uint32_t DCN_EXPANSION_MODE; \
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uint32_t DCHUBP_REQ_SIZE_CONFIG; \
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uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \
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uint32_t BLANK_OFFSET_0; \
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uint32_t BLANK_OFFSET_1; \
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uint32_t DST_DIMENSIONS; \
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uint32_t DST_AFTER_SCALER; \
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uint32_t PREFETCH_SETTINS; \
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uint32_t PREFETCH_SETTINGS; \
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uint32_t VBLANK_PARAMETERS_0; \
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uint32_t REF_FREQ_TO_PIX_FREQ; \
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uint32_t VBLANK_PARAMETERS_1; \
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uint32_t VBLANK_PARAMETERS_3; \
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uint32_t NOM_PARAMETERS_0; \
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uint32_t NOM_PARAMETERS_1; \
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uint32_t NOM_PARAMETERS_4; \
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uint32_t NOM_PARAMETERS_5; \
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uint32_t PER_LINE_DELIVERY_PRE; \
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uint32_t PER_LINE_DELIVERY; \
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uint32_t PREFETCH_SETTINS_C; \
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uint32_t PREFETCH_SETTINGS_C; \
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uint32_t VBLANK_PARAMETERS_2; \
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uint32_t VBLANK_PARAMETERS_4; \
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uint32_t NOM_PARAMETERS_2; \
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uint32_t NOM_PARAMETERS_3; \
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uint32_t NOM_PARAMETERS_6; \
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uint32_t NOM_PARAMETERS_7; \
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uint32_t DCN_TTU_QOS_WM; \
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uint32_t DCN_GLOBAL_TTU_CNTL; \
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uint32_t DCN_SURF0_TTU_CNTL0; \
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uint32_t DCN_SURF0_TTU_CNTL1; \
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uint32_t DCN_SURF1_TTU_CNTL0; \
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uint32_t DCN_SURF1_TTU_CNTL1; \
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uint32_t DCN_CUR0_TTU_CNTL0; \
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uint32_t DCN_CUR0_TTU_CNTL1; \
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uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \
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uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \
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uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
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uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \
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uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \
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uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \
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uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \
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uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \
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uint32_t DCN_VM_MX_L1_TLB_CNTL; \
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uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \
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uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \
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uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \
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uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \
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uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \
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uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \
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uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \
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uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \
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uint32_t CURSOR_SETTINS; \
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uint32_t CURSOR_SETTINGS; \
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uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \
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uint32_t CURSOR_SURFACE_ADDRESS; \
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uint32_t CURSOR_SIZE; \
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uint32_t CURSOR_CONTROL; \
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uint32_t CURSOR_POSITION; \
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uint32_t CURSOR_HOT_SPOT; \
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uint32_t CURSOR_DST_OFFSET; \
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uint32_t HUBP_CLK_CNTL
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#define HUBP_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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/* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
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/*1.x, 2.x, and 3.x*/
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#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
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HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
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HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
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HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
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HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
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HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
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HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
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HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
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HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
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HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
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HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
|
|
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
|
|
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
|
|
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
|
|
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
|
|
/*2.x and 1.x only*/
|
|
#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\
|
|
HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
|
|
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
|
|
|
|
/*2.x and 1.x only*/
|
|
#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
|
|
HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)
|
|
|
|
/* Mask/shift struct generation macro for ASICs with VM */
|
|
#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
|
|
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)
|
|
|
|
#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
|
|
HUBP_MASK_SH_LIST_DCN(mask_sh),\
|
|
HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
|
|
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
|
|
HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
|
|
HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
|
|
HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
|
|
|
|
#define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
|
|
type HUBP_BLANK_EN;\
|
|
type HUBP_DISABLE;\
|
|
type HUBP_TTU_DISABLE;\
|
|
type HUBP_NO_OUTSTANDING_REQ;\
|
|
type HUBP_VTG_SEL;\
|
|
type HUBP_UNDERFLOW_STATUS;\
|
|
type HUBP_UNDERFLOW_CLEAR;\
|
|
type HUBP_IN_BLANK;\
|
|
type NUM_PIPES;\
|
|
type NUM_BANKS;\
|
|
type PIPE_INTERLEAVE;\
|
|
type NUM_SE;\
|
|
type NUM_RB_PER_SE;\
|
|
type MAX_COMPRESSED_FRAGS;\
|
|
type SW_MODE;\
|
|
type META_LINEAR;\
|
|
type RB_ALIGNED;\
|
|
type PIPE_ALIGNED;\
|
|
type PITCH;\
|
|
type META_PITCH;\
|
|
type PITCH_C;\
|
|
type META_PITCH_C;\
|
|
type ROTATION_ANGLE;\
|
|
type H_MIRROR_EN;\
|
|
type SURFACE_PIXEL_FORMAT;\
|
|
type SURFACE_FLIP_TYPE;\
|
|
type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\
|
|
type SURFACE_FLIP_IN_STEREOSYNC;\
|
|
type SURFACE_UPDATE_LOCK;\
|
|
type SURFACE_FLIP_PENDING;\
|
|
type PRI_VIEWPORT_WIDTH; \
|
|
type PRI_VIEWPORT_HEIGHT; \
|
|
type PRI_VIEWPORT_X_START; \
|
|
type PRI_VIEWPORT_Y_START; \
|
|
type SEC_VIEWPORT_WIDTH; \
|
|
type SEC_VIEWPORT_HEIGHT; \
|
|
type SEC_VIEWPORT_X_START; \
|
|
type SEC_VIEWPORT_Y_START; \
|
|
type PRI_VIEWPORT_WIDTH_C; \
|
|
type PRI_VIEWPORT_HEIGHT_C; \
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type PRI_VIEWPORT_X_START_C; \
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type PRI_VIEWPORT_Y_START_C; \
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type SEC_VIEWPORT_WIDTH_C; \
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type SEC_VIEWPORT_HEIGHT_C; \
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type SEC_VIEWPORT_X_START_C; \
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type SEC_VIEWPORT_Y_START_C; \
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type PRIMARY_SURFACE_ADDRESS_HIGH;\
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type PRIMARY_SURFACE_ADDRESS;\
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type SECONDARY_SURFACE_ADDRESS_HIGH;\
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type SECONDARY_SURFACE_ADDRESS;\
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type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
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type PRIMARY_META_SURFACE_ADDRESS;\
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type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
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type SECONDARY_META_SURFACE_ADDRESS;\
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type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
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type PRIMARY_SURFACE_ADDRESS_C;\
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type SECONDARY_SURFACE_ADDRESS_HIGH_C;\
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type SECONDARY_SURFACE_ADDRESS_C;\
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type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
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type PRIMARY_META_SURFACE_ADDRESS_C;\
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type SECONDARY_META_SURFACE_ADDRESS_HIGH_C;\
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type SECONDARY_META_SURFACE_ADDRESS_C;\
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type SURFACE_INUSE_ADDRESS;\
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type SURFACE_INUSE_ADDRESS_HIGH;\
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type SURFACE_INUSE_ADDRESS_C;\
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type SURFACE_INUSE_ADDRESS_HIGH_C;\
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type SURFACE_EARLIEST_INUSE_ADDRESS;\
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type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\
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type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
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type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
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type PRIMARY_SURFACE_TMZ;\
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type PRIMARY_SURFACE_TMZ_C;\
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type SECONDARY_SURFACE_TMZ;\
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type SECONDARY_SURFACE_TMZ_C;\
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type PRIMARY_META_SURFACE_TMZ;\
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type PRIMARY_META_SURFACE_TMZ_C;\
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type SECONDARY_META_SURFACE_TMZ;\
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type SECONDARY_META_SURFACE_TMZ_C;\
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type PRIMARY_SURFACE_DCC_EN;\
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type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
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type SECONDARY_SURFACE_DCC_EN;\
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type SECONDARY_SURFACE_DCC_IND_64B_BLK;\
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type SURFACE_FLIP_INT_MASK;\
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type DET_BUF_PLANE1_BASE_ADDRESS;\
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type CROSSBAR_SRC_CB_B;\
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type CROSSBAR_SRC_CR_R;\
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type DRQ_EXPANSION_MODE;\
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type PRQ_EXPANSION_MODE;\
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type MRQ_EXPANSION_MODE;\
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type CRQ_EXPANSION_MODE;\
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type CHUNK_SIZE;\
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type MIN_CHUNK_SIZE;\
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type META_CHUNK_SIZE;\
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type MIN_META_CHUNK_SIZE;\
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type DPTE_GROUP_SIZE;\
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type MPTE_GROUP_SIZE;\
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type SWATH_HEIGHT;\
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type PTE_ROW_HEIGHT_LINEAR;\
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type CHUNK_SIZE_C;\
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type MIN_CHUNK_SIZE_C;\
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type META_CHUNK_SIZE_C;\
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type MIN_META_CHUNK_SIZE_C;\
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type DPTE_GROUP_SIZE_C;\
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type MPTE_GROUP_SIZE_C;\
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type SWATH_HEIGHT_C;\
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type PTE_ROW_HEIGHT_LINEAR_C;\
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type REFCYC_H_BLANK_END;\
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type DLG_V_BLANK_END;\
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type MIN_DST_Y_NEXT_START;\
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type REFCYC_PER_HTOTAL;\
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type REFCYC_X_AFTER_SCALER;\
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type DST_Y_AFTER_SCALER;\
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type DST_Y_PREFETCH;\
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type VRATIO_PREFETCH;\
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type DST_Y_PER_VM_VBLANK;\
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type DST_Y_PER_ROW_VBLANK;\
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type REF_FREQ_TO_PIX_FREQ;\
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type REFCYC_PER_PTE_GROUP_VBLANK_L;\
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type REFCYC_PER_META_CHUNK_VBLANK_L;\
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type DST_Y_PER_PTE_ROW_NOM_L;\
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type REFCYC_PER_PTE_GROUP_NOM_L;\
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type DST_Y_PER_META_ROW_NOM_L;\
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type REFCYC_PER_META_CHUNK_NOM_L;\
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type REFCYC_PER_LINE_DELIVERY_PRE_L;\
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type REFCYC_PER_LINE_DELIVERY_PRE_C;\
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type REFCYC_PER_LINE_DELIVERY_L;\
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type REFCYC_PER_LINE_DELIVERY_C;\
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type VRATIO_PREFETCH_C;\
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type REFCYC_PER_PTE_GROUP_VBLANK_C;\
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type REFCYC_PER_META_CHUNK_VBLANK_C;\
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type DST_Y_PER_PTE_ROW_NOM_C;\
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type REFCYC_PER_PTE_GROUP_NOM_C;\
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type DST_Y_PER_META_ROW_NOM_C;\
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type REFCYC_PER_META_CHUNK_NOM_C;\
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type QoS_LEVEL_LOW_WM;\
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type QoS_LEVEL_HIGH_WM;\
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type MIN_TTU_VBLANK;\
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type QoS_LEVEL_FLIP;\
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type REFCYC_PER_REQ_DELIVERY;\
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type QoS_LEVEL_FIXED;\
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type QoS_RAMP_DISABLE;\
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type REFCYC_PER_REQ_DELIVERY_PRE;\
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type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
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type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
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type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
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type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
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type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
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type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
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type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
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type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\
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type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
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type ENABLE_L1_TLB;\
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type SYSTEM_ACCESS_MODE;\
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type HUBP_CLOCK_ENABLE;\
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type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
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type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
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type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
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type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
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type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
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type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
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type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
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type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
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type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
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type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
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type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
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type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
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/* todo: get these from GVM instead of reading registers ourselves */\
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type PAGE_DIRECTORY_ENTRY_HI32;\
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type PAGE_DIRECTORY_ENTRY_LO32;\
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type LOGICAL_PAGE_NUMBER_HI4;\
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type LOGICAL_PAGE_NUMBER_LO32;\
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type PHYSICAL_PAGE_ADDR_HI4;\
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type PHYSICAL_PAGE_ADDR_LO32;\
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type PHYSICAL_PAGE_NUMBER_MSB;\
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type PHYSICAL_PAGE_NUMBER_LSB;\
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type LOGICAL_ADDR;\
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type CURSOR0_DST_Y_OFFSET; \
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type CURSOR0_CHUNK_HDL_ADJUST; \
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type CURSOR_SURFACE_ADDRESS_HIGH; \
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type CURSOR_SURFACE_ADDRESS; \
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type CURSOR_WIDTH; \
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type CURSOR_HEIGHT; \
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type CURSOR_MODE; \
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type CURSOR_2X_MAGNIFY; \
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type CURSOR_PITCH; \
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type CURSOR_LINES_PER_CHUNK; \
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type CURSOR_ENABLE; \
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type CURSOR_X_POSITION; \
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type CURSOR_Y_POSITION; \
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type CURSOR_HOT_SPOT_X; \
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type CURSOR_HOT_SPOT_Y; \
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type CURSOR_DST_X_OFFSET; \
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type OUTPUT_FP
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|
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#define DCN_HUBP_REG_FIELD_LIST(type) \
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DCN_HUBP_REG_FIELD_BASE_LIST(type);\
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type ALPHA_PLANE_EN
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|
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struct dcn_mi_registers {
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HUBP_COMMON_REG_VARIABLE_LIST;
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};
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struct dcn_mi_shift {
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DCN_HUBP_REG_FIELD_LIST(uint8_t);
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};
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struct dcn_mi_mask {
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DCN_HUBP_REG_FIELD_LIST(uint32_t);
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};
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struct dcn_hubp_state {
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struct _vcs_dpi_display_dlg_regs_st dlg_attr;
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|
struct _vcs_dpi_display_ttu_regs_st ttu_attr;
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|
struct _vcs_dpi_display_rq_regs_st rq_regs;
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|
uint32_t pixel_format;
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|
uint32_t inuse_addr_hi;
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|
uint32_t inuse_addr_lo;
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|
uint32_t viewport_width;
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|
uint32_t viewport_height;
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|
uint32_t rotation_angle;
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|
uint32_t h_mirror_en;
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|
uint32_t sw_mode;
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|
uint32_t dcc_en;
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|
uint32_t blank_en;
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|
uint32_t clock_en;
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|
uint32_t underflow_status;
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|
uint32_t ttu_disable;
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|
uint32_t min_ttu_vblank;
|
|
uint32_t qos_level_low_wm;
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|
uint32_t qos_level_high_wm;
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|
};
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|
|
|
struct dcn10_hubp {
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|
struct hubp base;
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|
struct dcn_hubp_state state;
|
|
const struct dcn_mi_registers *hubp_regs;
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|
const struct dcn_mi_shift *hubp_shift;
|
|
const struct dcn_mi_mask *hubp_mask;
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|
};
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|
|
|
void hubp1_program_surface_config(
|
|
struct hubp *hubp,
|
|
enum surface_pixel_format format,
|
|
union dc_tiling_info *tiling_info,
|
|
struct plane_size *plane_size,
|
|
enum dc_rotation_angle rotation,
|
|
struct dc_plane_dcc_param *dcc,
|
|
bool horizontal_mirror,
|
|
unsigned int compat_level);
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|
|
|
void hubp1_program_deadline(
|
|
struct hubp *hubp,
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|
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
|
|
struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
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|
|
|
void hubp1_program_requestor(
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|
struct hubp *hubp,
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|
struct _vcs_dpi_display_rq_regs_st *rq_regs);
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|
|
|
void hubp1_program_pixel_format(
|
|
struct hubp *hubp,
|
|
enum surface_pixel_format format);
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|
|
|
void hubp1_program_size(
|
|
struct hubp *hubp,
|
|
enum surface_pixel_format format,
|
|
const struct plane_size *plane_size,
|
|
struct dc_plane_dcc_param *dcc);
|
|
|
|
void hubp1_program_rotation(
|
|
struct hubp *hubp,
|
|
enum dc_rotation_angle rotation,
|
|
bool horizontal_mirror);
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|
|
|
void hubp1_program_tiling(
|
|
struct hubp *hubp,
|
|
const union dc_tiling_info *info,
|
|
const enum surface_pixel_format pixel_format);
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|
|
|
void hubp1_dcc_control(struct hubp *hubp,
|
|
bool enable,
|
|
enum hubp_ind_block_size independent_64b_blks);
|
|
|
|
bool hubp1_program_surface_flip_and_addr(
|
|
struct hubp *hubp,
|
|
const struct dc_plane_address *address,
|
|
bool flip_immediate);
|
|
|
|
bool hubp1_is_flip_pending(struct hubp *hubp);
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|
|
|
void hubp1_cursor_set_attributes(
|
|
struct hubp *hubp,
|
|
const struct dc_cursor_attributes *attr);
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|
|
|
void hubp1_cursor_set_position(
|
|
struct hubp *hubp,
|
|
const struct dc_cursor_position *pos,
|
|
const struct dc_cursor_mi_param *param);
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|
|
|
void hubp1_set_blank(struct hubp *hubp, bool blank);
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|
|
|
void min_set_viewport(struct hubp *hubp,
|
|
const struct rect *viewport,
|
|
const struct rect *viewport_c);
|
|
|
|
void hubp1_clk_cntl(struct hubp *hubp, bool enable);
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|
void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
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|
|
|
void dcn10_hubp_construct(
|
|
struct dcn10_hubp *hubp1,
|
|
struct dc_context *ctx,
|
|
uint32_t inst,
|
|
const struct dcn_mi_registers *hubp_regs,
|
|
const struct dcn_mi_shift *hubp_shift,
|
|
const struct dcn_mi_mask *hubp_mask);
|
|
|
|
void hubp1_read_state(struct hubp *hubp);
|
|
void hubp1_clear_underflow(struct hubp *hubp);
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|
|
|
enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
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|
|
|
void hubp1_vready_workaround(struct hubp *hubp,
|
|
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
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|
|
|
void hubp1_init(struct hubp *hubp);
|
|
void hubp1_read_state_common(struct hubp *hubp);
|
|
bool hubp1_in_blank(struct hubp *hubp);
|
|
void hubp1_soft_reset(struct hubp *hubp, bool reset);
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|
|
void hubp1_set_flip_int(struct hubp *hubp);
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|
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#endif
|