d11219ad53
The DRM_AMD_DC_DCN display engine support (Raven, Navi, and newer) has not been building cleanly on powerpc and causes link errors due to mixing hard- and soft-float object files: powerpc64-linux-ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o uses soft float powerpc64-linux-ld: failed to merge target specific data of file drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o [..] and while patches are floating around, it's not exactly obvious what is going on. The problem bisects to commit41b7a347bf("powerpc: Book3S 64-bit outline-only KASAN support") but that is probably more about changing config variables than the fundamental cause. Despite the bisection result, a more directly related commit seems to be26f4712aed("drm/amd/display: move FPU related code from dcn31 to dml/dcn31 folder"). It's probably a combination of the two. This has been going on since the merge window, without any final word. So instead of blindly applying patches that may or may not be the right thing, let's disable this for now. As Michael Ellerman says: "IIUIC this code was never enabled on ppc before, so disabling it seems like a reasonable fix to get the build clean" and once we have more actual feedback (and find any potential users) we can always re-enable it with the patch that fixes the issues and back-port as necessary. Fixes:41b7a347bf("powerpc: Book3S 64-bit outline-only KASAN support") Fixes:26f4712aed("drm/amd/display: move FPU related code from dcn31 to dml/dcn31 folder") Reported-and-tested-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/all/20220606153910.GA1773067@roeck-us.net/ Link: https://lore.kernel.org/all/20220618232737.2036722-1-linux@roeck-us.net/ Link: https://lore.kernel.org/all/20220713050724.GA2471738@roeck-us.net/ Acked-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
59 lines
1.6 KiB
Plaintext
59 lines
1.6 KiB
Plaintext
# SPDX-License-Identifier: MIT
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menu "Display Engine Configuration"
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depends on DRM && DRM_AMDGPU
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config DRM_AMD_DC
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bool "AMD DC - Enable new display engine"
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default y
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select SND_HDA_COMPONENT if SND_HDA_CORE
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select DRM_AMD_DC_DCN if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
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help
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Choose this option if you want to use the new display engine
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support for AMDGPU. This adds required support for Vega and
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Raven ASICs.
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config DRM_AMD_DC_DCN
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def_bool n
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help
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Raven, Navi, and newer family support for display engine
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config DRM_AMD_DC_HDCP
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bool "Enable HDCP support in DC"
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depends on DRM_AMD_DC
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select DRM_DISPLAY_HDCP_HELPER
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help
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Choose this option if you want to support HDCP authentication.
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config DRM_AMD_DC_SI
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bool "AMD DC support for Southern Islands ASICs"
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depends on DRM_AMDGPU_SI
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depends on DRM_AMD_DC
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default n
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help
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Choose this option to enable new AMD DC support for SI asics
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by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.
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Hainan is not supported by AMD DC and it has no physical DCE6.
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config DEBUG_KERNEL_DC
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bool "Enable kgdb break in DC"
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depends on DRM_AMD_DC
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depends on KGDB
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help
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Choose this option if you want to hit kdgb_break in assert.
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config DRM_AMD_SECURE_DISPLAY
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bool "Enable secure display support"
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default n
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depends on DEBUG_FS
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depends on DRM_AMD_DC_DCN
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help
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Choose this option if you want to
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support secure display
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This option enables the calculation
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of crc of specific region via debugfs.
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Cooperate with specific DMCU FW.
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endmenu
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