Sung Lee a19620ea91 drm/amd/display: Program self refresh control register on boot ... [WHY] In headless boot cases, self refresh control registers are not programmed on boot. In certain hybrid graphics cases this may cause cstate entering to get blocked causing a hang. [HOW] Program self refresh control register on boot. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-03-19 00:03:04 -04:00
..
amdgpu_dm	drm/amd/display: Remove PSR dependency on swizzle mode	2020-03-19 00:03:04 -04:00
dc	drm/amd/display: Program self refresh control register on boot	2020-03-19 00:03:04 -04:00
dmub	drm/amd/display: Add ABM command structs to DMCUB	2020-03-05 00:31:31 -05:00
include	drm/amdgpu/display: Fix Pollock Variant Detection	2020-03-09 13:51:03 -04:00
modules	drm/amd/display: remove magic numbers in hdcp_ddc	2020-03-19 00:03:04 -04:00
Kconfig	amdgpu: Enable initial DCN support on POWER	2019-12-18 16:09:05 -05:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards	2019-11-13 15:29:42 -05:00
TODO