ab07725abc
The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges additionally to the typical values for pixel clock rate (64.3-82 MHz) and blanking intervals (54-681 clock cycles horizontally, 3-23 lines vertically). This patch replaces this panel's display mode with the display timing information to describe acceptable timings. Since the HSYNC and VSYNC are unused, the distribution between front porches, back porches, and sync pulse lengths was chosen at will. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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| drm | ||
| host1x | ||
| ipu-v3 | ||
| vga | ||
| Makefile | ||