Ben Skeggs 9bd2ddbaa2 drm/nouveau/fifo/nvc0-: use interrupt 31 as an event trigger ... Generated if you try and use fifo method 0x20 on any subchannel, appears that it can be safely masked off without stalling the whole GPU. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>		2013-02-20 16:00:46 +10:00
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bsp	nvc0/bsp: initial implementation of engine	2012-11-29 09:58:07 +10:00
copy	drm/nouveau: report channel owner in error messages	2013-02-20 16:00:33 +10:00
crypt	drm/nouveau: mark nv_printk_ as printf-like function	2013-02-20 16:00:34 +10:00
disp	drm/nouveau/disp: port vblank handling to event interface	2013-02-20 16:00:46 +10:00
dmaobj	drm/nvd0-nve0/disp: initial implementation of evo channel classes	2012-11-29 09:57:40 +10:00
fifo	drm/nouveau/fifo/nvc0-: use interrupt 31 as an event trigger	2013-02-20 16:00:46 +10:00
graph	drm/nvc0/graph: remove redundant null checks	2013-02-20 16:00:37 +10:00
mpeg	drm/nouveau: report channel owner in error messages	2013-02-20 16:00:33 +10:00
ppp	drm/nouveau/ppp: remove nouveau_ppp base class	2012-11-29 09:58:09 +10:00
software	drm/nouveau/disp: port vblank handling to event interface	2013-02-20 16:00:46 +10:00
vp	nvc0/vp: initial implementation of engine	2012-11-29 09:58:07 +10:00