Shaoyun Liu 984564031a drm/amd/include: update the bitfield define for PF_MAX_REGION ... Correct the definition based on vega20 register spec Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-09-10 22:45:51 -05:00
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gc_9_0_default.h	drm/amdgpu: remove some old gc 9.x registers	2017-12-13 17:28:08 -05:00
gc_9_0_offset.h	drm/amdgpu: remove some old gc 9.x registers	2017-12-13 17:28:08 -05:00
gc_9_0_sh_mask.h	drm/amdgpu: remove some old gc 9.x registers	2017-12-13 17:28:08 -05:00
gc_9_1_offset.h	drm/amdgpu: remove some old gc 9.x registers	2017-12-13 17:28:08 -05:00
gc_9_1_sh_mask.h	drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header files	2018-03-07 16:10:13 -05:00
gc_9_2_1_offset.h	drm/amd/include: Add ip header files for vega12.	2018-03-21 14:23:01 -05:00
gc_9_2_1_sh_mask.h	drm/amd/include: update the bitfield define for PF_MAX_REGION	2018-09-10 22:45:51 -05:00