forked from Minki/linux
e2f748e06d
Up until now PIO mode offered only playback support. With this patch we add support for record mode. The PCM was refactored so that we could reuse the existing infrastructure without many changes. We have support for 16 and 32 bits of sample size using only 2 channels. Tested in a x86_64 platform and in ARC AXS101 SDP platform. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Mark Brown <broonie@kernel.org>
136 lines
4.0 KiB
C
136 lines
4.0 KiB
C
/*
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* Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __DESIGNWARE_LOCAL_H
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#define __DESIGNWARE_LOCAL_H
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/types.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm.h>
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#include <sound/designware_i2s.h>
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/* common register for all channel */
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#define IER 0x000
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#define IRER 0x004
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#define ITER 0x008
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#define CER 0x00C
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#define CCR 0x010
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#define RXFFR 0x014
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#define TXFFR 0x018
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/* Interrupt status register fields */
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#define ISR_TXFO BIT(5)
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#define ISR_TXFE BIT(4)
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#define ISR_RXFO BIT(1)
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#define ISR_RXDA BIT(0)
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/* I2STxRxRegisters for all channels */
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#define LRBR_LTHR(x) (0x40 * x + 0x020)
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#define RRBR_RTHR(x) (0x40 * x + 0x024)
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#define RER(x) (0x40 * x + 0x028)
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#define TER(x) (0x40 * x + 0x02C)
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#define RCR(x) (0x40 * x + 0x030)
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#define TCR(x) (0x40 * x + 0x034)
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#define ISR(x) (0x40 * x + 0x038)
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#define IMR(x) (0x40 * x + 0x03C)
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#define ROR(x) (0x40 * x + 0x040)
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#define TOR(x) (0x40 * x + 0x044)
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#define RFCR(x) (0x40 * x + 0x048)
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#define TFCR(x) (0x40 * x + 0x04C)
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#define RFF(x) (0x40 * x + 0x050)
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#define TFF(x) (0x40 * x + 0x054)
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/* I2SCOMPRegisters */
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#define I2S_COMP_PARAM_2 0x01F0
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#define I2S_COMP_PARAM_1 0x01F4
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#define I2S_COMP_VERSION 0x01F8
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#define I2S_COMP_TYPE 0x01FC
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/*
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* Component parameter register fields - define the I2S block's
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* configuration.
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*/
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#define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25)
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#define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22)
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#define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19)
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#define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16)
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#define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9)
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#define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7)
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#define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6)
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#define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5)
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#define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4)
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#define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2)
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#define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)
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#define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10)
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#define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7)
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#define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3)
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#define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0)
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/* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
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#define COMP_MAX_WORDSIZE (1 << 3)
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#define COMP_MAX_DATA_WIDTH (1 << 2)
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#define MAX_CHANNEL_NUM 8
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#define MIN_CHANNEL_NUM 2
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union dw_i2s_snd_dma_data {
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struct i2s_dma_data pd;
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struct snd_dmaengine_dai_dma_data dt;
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};
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struct dw_i2s_dev {
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void __iomem *i2s_base;
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struct clk *clk;
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int active;
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unsigned int capability;
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unsigned int quirks;
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unsigned int i2s_reg_comp1;
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unsigned int i2s_reg_comp2;
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struct device *dev;
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u32 ccr;
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u32 xfer_resolution;
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u32 fifo_th;
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/* data related to DMA transfers b/w i2s and DMAC */
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union dw_i2s_snd_dma_data play_dma_data;
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union dw_i2s_snd_dma_data capture_dma_data;
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struct i2s_clk_config_data config;
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int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
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/* data related to PIO transfers */
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bool use_pio;
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struct snd_pcm_substream __rcu *tx_substream;
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struct snd_pcm_substream __rcu *rx_substream;
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unsigned int (*tx_fn)(struct dw_i2s_dev *dev,
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struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
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bool *period_elapsed);
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unsigned int (*rx_fn)(struct dw_i2s_dev *dev,
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struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
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bool *period_elapsed);
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unsigned int tx_ptr;
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unsigned int rx_ptr;
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};
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#if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM)
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void dw_pcm_push_tx(struct dw_i2s_dev *dev);
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void dw_pcm_pop_rx(struct dw_i2s_dev *dev);
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int dw_pcm_register(struct platform_device *pdev);
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#else
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void dw_pcm_push_tx(struct dw_i2s_dev *dev) { }
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void dw_pcm_pop_rx(struct dw_i2s_dev *dev) { }
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int dw_pcm_register(struct platform_device *pdev)
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{
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return -EINVAL;
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}
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#endif
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#endif
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