forked from Minki/linux
ac422f9443
Wrapping pr_fmt to the KBUILD_MODNAME prefix seems to be the trendy thing to do these days, so just do that instead of manually tidying up the stragglers. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
1391 lines
33 KiB
C
1391 lines
33 KiB
C
/*
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* Shared interrupt handling code for IPR and INTC2 types of IRQs.
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*
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* Copyright (C) 2007, 2008 Magnus Damm
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* Copyright (C) 2009, 2010 Paul Mundt
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*
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* Based on intc2.c and ipr.c
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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* Copyright (C) 2005, 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/sh_intc.h>
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#include <linux/sysdev.h>
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#include <linux/list.h>
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#include <linux/topology.h>
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#include <linux/bitmap.h>
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#include <linux/cpumask.h>
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#include <asm/sizes.h>
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#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
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((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
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((addr_e) << 16) | ((addr_d << 24)))
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#define _INTC_SHIFT(h) (h & 0x1f)
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#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
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#define _INTC_FN(h) ((h >> 9) & 0xf)
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#define _INTC_MODE(h) ((h >> 13) & 0x7)
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#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
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#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
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struct intc_handle_int {
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unsigned int irq;
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unsigned long handle;
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};
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struct intc_window {
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phys_addr_t phys;
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void __iomem *virt;
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unsigned long size;
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};
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struct intc_desc_int {
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struct list_head list;
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struct sys_device sysdev;
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pm_message_t state;
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unsigned long *reg;
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#ifdef CONFIG_SMP
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unsigned long *smp;
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#endif
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unsigned int nr_reg;
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struct intc_handle_int *prio;
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unsigned int nr_prio;
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struct intc_handle_int *sense;
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unsigned int nr_sense;
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struct intc_window *window;
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unsigned int nr_windows;
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struct irq_chip chip;
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};
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static LIST_HEAD(intc_list);
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/*
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* The intc_irq_map provides a global map of bound IRQ vectors for a
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* given platform. Allocation of IRQs are either static through the CPU
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* vector map, or dynamic in the case of board mux vectors or MSI.
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*
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* As this is a central point for all IRQ controllers on the system,
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* each of the available sources are mapped out here. This combined with
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* sparseirq makes it quite trivial to keep the vector map tightly packed
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* when dynamically creating IRQs, as well as tying in to otherwise
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* unused irq_desc positions in the sparse array.
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*/
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static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
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static DEFINE_SPINLOCK(vector_lock);
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#ifdef CONFIG_SMP
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#define IS_SMP(x) x.smp
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#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
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#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
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#else
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#define IS_SMP(x) 0
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#define INTC_REG(d, x, c) (d->reg[(x)])
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#define SMP_NR(d, x) 1
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#endif
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static unsigned int intc_prio_level[NR_IRQS]; /* for now */
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static unsigned int default_prio_level = 2; /* 2 - 16 */
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static unsigned long ack_handle[NR_IRQS];
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#ifdef CONFIG_INTC_BALANCING
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static unsigned long dist_handle[NR_IRQS];
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#endif
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static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
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{
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struct irq_chip *chip = get_irq_chip(irq);
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return container_of(chip, struct intc_desc_int, chip);
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}
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static unsigned long intc_phys_to_virt(struct intc_desc_int *d,
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unsigned long address)
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{
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struct intc_window *window;
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int k;
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/* scan through physical windows and convert address */
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for (k = 0; k < d->nr_windows; k++) {
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window = d->window + k;
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if (address < window->phys)
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continue;
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if (address >= (window->phys + window->size))
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continue;
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address -= window->phys;
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address += (unsigned long)window->virt;
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return address;
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}
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/* no windows defined, register must be 1:1 mapped virt:phys */
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return address;
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}
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static unsigned int intc_get_reg(struct intc_desc_int *d, unsigned long address)
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{
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unsigned int k;
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address = intc_phys_to_virt(d, address);
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for (k = 0; k < d->nr_reg; k++) {
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if (d->reg[k] == address)
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return k;
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}
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BUG();
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return 0;
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}
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static inline unsigned int set_field(unsigned int value,
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unsigned int field_value,
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unsigned int handle)
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{
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unsigned int width = _INTC_WIDTH(handle);
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unsigned int shift = _INTC_SHIFT(handle);
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value &= ~(((1 << width) - 1) << shift);
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value |= field_value << shift;
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return value;
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}
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static void write_8(unsigned long addr, unsigned long h, unsigned long data)
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{
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__raw_writeb(set_field(0, data, h), addr);
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(void)__raw_readb(addr); /* Defeat write posting */
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}
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static void write_16(unsigned long addr, unsigned long h, unsigned long data)
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{
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__raw_writew(set_field(0, data, h), addr);
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(void)__raw_readw(addr); /* Defeat write posting */
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}
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static void write_32(unsigned long addr, unsigned long h, unsigned long data)
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{
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__raw_writel(set_field(0, data, h), addr);
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(void)__raw_readl(addr); /* Defeat write posting */
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}
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static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
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{
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unsigned long flags;
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local_irq_save(flags);
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__raw_writeb(set_field(__raw_readb(addr), data, h), addr);
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(void)__raw_readb(addr); /* Defeat write posting */
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local_irq_restore(flags);
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}
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static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
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{
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unsigned long flags;
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local_irq_save(flags);
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__raw_writew(set_field(__raw_readw(addr), data, h), addr);
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(void)__raw_readw(addr); /* Defeat write posting */
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local_irq_restore(flags);
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}
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static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
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{
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unsigned long flags;
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local_irq_save(flags);
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__raw_writel(set_field(__raw_readl(addr), data, h), addr);
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(void)__raw_readl(addr); /* Defeat write posting */
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local_irq_restore(flags);
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}
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enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
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static void (*intc_reg_fns[])(unsigned long addr,
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unsigned long h,
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unsigned long data) = {
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[REG_FN_WRITE_BASE + 0] = write_8,
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[REG_FN_WRITE_BASE + 1] = write_16,
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[REG_FN_WRITE_BASE + 3] = write_32,
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[REG_FN_MODIFY_BASE + 0] = modify_8,
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[REG_FN_MODIFY_BASE + 1] = modify_16,
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[REG_FN_MODIFY_BASE + 3] = modify_32,
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};
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enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
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MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
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MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
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MODE_PRIO_REG, /* Priority value written to enable interrupt */
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MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
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};
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static void intc_mode_field(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq)
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{
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fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
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}
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static void intc_mode_zero(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq)
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{
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fn(addr, handle, 0);
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}
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static void intc_mode_prio(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq)
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{
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fn(addr, handle, intc_prio_level[irq]);
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}
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static void (*intc_enable_fns[])(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq) = {
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[MODE_ENABLE_REG] = intc_mode_field,
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[MODE_MASK_REG] = intc_mode_zero,
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[MODE_DUAL_REG] = intc_mode_field,
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[MODE_PRIO_REG] = intc_mode_prio,
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[MODE_PCLR_REG] = intc_mode_prio,
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};
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static void (*intc_disable_fns[])(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq) = {
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[MODE_ENABLE_REG] = intc_mode_zero,
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[MODE_MASK_REG] = intc_mode_field,
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[MODE_DUAL_REG] = intc_mode_field,
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[MODE_PRIO_REG] = intc_mode_zero,
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[MODE_PCLR_REG] = intc_mode_field,
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};
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#ifdef CONFIG_INTC_BALANCING
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static inline void intc_balancing_enable(unsigned int irq)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long handle = dist_handle[irq];
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unsigned long addr;
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if (irq_balancing_disabled(irq) || !handle)
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return;
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addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
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intc_reg_fns[_INTC_FN(handle)](addr, handle, 1);
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}
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static inline void intc_balancing_disable(unsigned int irq)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long handle = dist_handle[irq];
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unsigned long addr;
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if (irq_balancing_disabled(irq) || !handle)
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return;
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addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
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intc_reg_fns[_INTC_FN(handle)](addr, handle, 0);
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}
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static unsigned int intc_dist_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id)
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{
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struct intc_mask_reg *mr = desc->hw.mask_regs;
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unsigned int i, j, fn, mode;
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unsigned long reg_e, reg_d;
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for (i = 0; mr && enum_id && i < desc->hw.nr_mask_regs; i++) {
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mr = desc->hw.mask_regs + i;
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/*
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* Skip this entry if there's no auto-distribution
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* register associated with it.
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*/
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if (!mr->dist_reg)
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continue;
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for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
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if (mr->enum_ids[j] != enum_id)
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continue;
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fn = REG_FN_MODIFY_BASE;
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mode = MODE_ENABLE_REG;
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reg_e = mr->dist_reg;
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reg_d = mr->dist_reg;
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fn += (mr->reg_width >> 3) - 1;
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return _INTC_MK(fn, mode,
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intc_get_reg(d, reg_e),
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intc_get_reg(d, reg_d),
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1,
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(mr->reg_width - 1) - j);
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}
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}
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/*
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* It's possible we've gotten here with no distribution options
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* available for the IRQ in question, so we just skip over those.
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*/
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return 0;
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}
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#else
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static inline void intc_balancing_enable(unsigned int irq)
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{
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}
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static inline void intc_balancing_disable(unsigned int irq)
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{
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}
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#endif
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static inline void _intc_enable(unsigned int irq, unsigned long handle)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long addr;
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unsigned int cpu;
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
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#ifdef CONFIG_SMP
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if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
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continue;
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#endif
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addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
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intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
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[_INTC_FN(handle)], irq);
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}
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intc_balancing_enable(irq);
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}
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static void intc_enable(unsigned int irq)
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{
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_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
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}
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static void intc_disable(unsigned int irq)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long handle = (unsigned long)get_irq_chip_data(irq);
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unsigned long addr;
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unsigned int cpu;
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intc_balancing_disable(irq);
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
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#ifdef CONFIG_SMP
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if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
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continue;
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#endif
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addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
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intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
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[_INTC_FN(handle)], irq);
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}
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}
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static void (*intc_enable_noprio_fns[])(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq) = {
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[MODE_ENABLE_REG] = intc_mode_field,
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[MODE_MASK_REG] = intc_mode_zero,
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[MODE_DUAL_REG] = intc_mode_field,
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[MODE_PRIO_REG] = intc_mode_field,
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[MODE_PCLR_REG] = intc_mode_field,
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};
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|
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static void intc_enable_disable(struct intc_desc_int *d,
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unsigned long handle, int do_enable)
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{
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unsigned long addr;
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unsigned int cpu;
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void (*fn)(unsigned long, unsigned long,
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void (*)(unsigned long, unsigned long, unsigned long),
|
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unsigned int);
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|
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if (do_enable) {
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
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addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
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fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
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fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
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}
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} else {
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
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addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
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fn = intc_disable_fns[_INTC_MODE(handle)];
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fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
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}
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}
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}
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|
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static int intc_set_wake(unsigned int irq, unsigned int on)
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|
{
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return 0; /* allow wakeup, but setup hardware in intc_suspend() */
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}
|
|
|
|
#ifdef CONFIG_SMP
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|
/*
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* This is held with the irq desc lock held, so we don't require any
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* additional locking here at the intc desc level. The affinity mask is
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* later tested in the enable/disable paths.
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*/
|
|
static int intc_set_affinity(unsigned int irq, const struct cpumask *cpumask)
|
|
{
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if (!cpumask_intersects(cpumask, cpu_online_mask))
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return -1;
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cpumask_copy(irq_to_desc(irq)->affinity, cpumask);
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return 0;
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}
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#endif
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static void intc_mask_ack(unsigned int irq)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long handle = ack_handle[irq];
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unsigned long addr;
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intc_disable(irq);
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/* read register and write zero only to the associated bit */
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if (handle) {
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addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
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switch (_INTC_FN(handle)) {
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case REG_FN_MODIFY_BASE + 0: /* 8bit */
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__raw_readb(addr);
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__raw_writeb(0xff ^ set_field(0, 1, handle), addr);
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break;
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case REG_FN_MODIFY_BASE + 1: /* 16bit */
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__raw_readw(addr);
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__raw_writew(0xffff ^ set_field(0, 1, handle), addr);
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break;
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case REG_FN_MODIFY_BASE + 3: /* 32bit */
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__raw_readl(addr);
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__raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
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break;
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default:
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BUG();
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break;
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|
}
|
|
}
|
|
}
|
|
|
|
static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
|
|
unsigned int nr_hp,
|
|
unsigned int irq)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* this doesn't scale well, but...
|
|
*
|
|
* this function should only be used for cerain uncommon
|
|
* operations such as intc_set_priority() and intc_set_sense()
|
|
* and in those rare cases performance doesn't matter that much.
|
|
* keeping the memory footprint low is more important.
|
|
*
|
|
* one rather simple way to speed this up and still keep the
|
|
* memory footprint down is to make sure the array is sorted
|
|
* and then perform a bisect to lookup the irq.
|
|
*/
|
|
for (i = 0; i < nr_hp; i++) {
|
|
if ((hp + i)->irq != irq)
|
|
continue;
|
|
|
|
return hp + i;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
int intc_set_priority(unsigned int irq, unsigned int prio)
|
|
{
|
|
struct intc_desc_int *d = get_intc_desc(irq);
|
|
struct intc_handle_int *ihp;
|
|
|
|
if (!intc_prio_level[irq] || prio <= 1)
|
|
return -EINVAL;
|
|
|
|
ihp = intc_find_irq(d->prio, d->nr_prio, irq);
|
|
if (ihp) {
|
|
if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
|
|
return -EINVAL;
|
|
|
|
intc_prio_level[irq] = prio;
|
|
|
|
/*
|
|
* only set secondary masking method directly
|
|
* primary masking method is using intc_prio_level[irq]
|
|
* priority level will be set during next enable()
|
|
*/
|
|
if (_INTC_FN(ihp->handle) != REG_FN_ERR)
|
|
_intc_enable(irq, ihp->handle);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#define VALID(x) (x | 0x80)
|
|
|
|
static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
|
|
[IRQ_TYPE_EDGE_FALLING] = VALID(0),
|
|
[IRQ_TYPE_EDGE_RISING] = VALID(1),
|
|
[IRQ_TYPE_LEVEL_LOW] = VALID(2),
|
|
/* SH7706, SH7707 and SH7709 do not support high level triggered */
|
|
#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
|
|
!defined(CONFIG_CPU_SUBTYPE_SH7707) && \
|
|
!defined(CONFIG_CPU_SUBTYPE_SH7709)
|
|
[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
|
|
#endif
|
|
};
|
|
|
|
static int intc_set_sense(unsigned int irq, unsigned int type)
|
|
{
|
|
struct intc_desc_int *d = get_intc_desc(irq);
|
|
unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
|
|
struct intc_handle_int *ihp;
|
|
unsigned long addr;
|
|
|
|
if (!value)
|
|
return -EINVAL;
|
|
|
|
ihp = intc_find_irq(d->sense, d->nr_sense, irq);
|
|
if (ihp) {
|
|
addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
|
|
intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static intc_enum __init intc_grp_id(struct intc_desc *desc,
|
|
intc_enum enum_id)
|
|
{
|
|
struct intc_group *g = desc->hw.groups;
|
|
unsigned int i, j;
|
|
|
|
for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
|
|
g = desc->hw.groups + i;
|
|
|
|
for (j = 0; g->enum_ids[j]; j++) {
|
|
if (g->enum_ids[j] != enum_id)
|
|
continue;
|
|
|
|
return g->enum_id;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int __init _intc_mask_data(struct intc_desc *desc,
|
|
struct intc_desc_int *d,
|
|
intc_enum enum_id,
|
|
unsigned int *reg_idx,
|
|
unsigned int *fld_idx)
|
|
{
|
|
struct intc_mask_reg *mr = desc->hw.mask_regs;
|
|
unsigned int fn, mode;
|
|
unsigned long reg_e, reg_d;
|
|
|
|
while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
|
|
mr = desc->hw.mask_regs + *reg_idx;
|
|
|
|
for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
|
|
if (mr->enum_ids[*fld_idx] != enum_id)
|
|
continue;
|
|
|
|
if (mr->set_reg && mr->clr_reg) {
|
|
fn = REG_FN_WRITE_BASE;
|
|
mode = MODE_DUAL_REG;
|
|
reg_e = mr->clr_reg;
|
|
reg_d = mr->set_reg;
|
|
} else {
|
|
fn = REG_FN_MODIFY_BASE;
|
|
if (mr->set_reg) {
|
|
mode = MODE_ENABLE_REG;
|
|
reg_e = mr->set_reg;
|
|
reg_d = mr->set_reg;
|
|
} else {
|
|
mode = MODE_MASK_REG;
|
|
reg_e = mr->clr_reg;
|
|
reg_d = mr->clr_reg;
|
|
}
|
|
}
|
|
|
|
fn += (mr->reg_width >> 3) - 1;
|
|
return _INTC_MK(fn, mode,
|
|
intc_get_reg(d, reg_e),
|
|
intc_get_reg(d, reg_d),
|
|
1,
|
|
(mr->reg_width - 1) - *fld_idx);
|
|
}
|
|
|
|
*fld_idx = 0;
|
|
(*reg_idx)++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int __init intc_mask_data(struct intc_desc *desc,
|
|
struct intc_desc_int *d,
|
|
intc_enum enum_id, int do_grps)
|
|
{
|
|
unsigned int i = 0;
|
|
unsigned int j = 0;
|
|
unsigned int ret;
|
|
|
|
ret = _intc_mask_data(desc, d, enum_id, &i, &j);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (do_grps)
|
|
return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int __init _intc_prio_data(struct intc_desc *desc,
|
|
struct intc_desc_int *d,
|
|
intc_enum enum_id,
|
|
unsigned int *reg_idx,
|
|
unsigned int *fld_idx)
|
|
{
|
|
struct intc_prio_reg *pr = desc->hw.prio_regs;
|
|
unsigned int fn, n, mode, bit;
|
|
unsigned long reg_e, reg_d;
|
|
|
|
while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
|
|
pr = desc->hw.prio_regs + *reg_idx;
|
|
|
|
for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
|
|
if (pr->enum_ids[*fld_idx] != enum_id)
|
|
continue;
|
|
|
|
if (pr->set_reg && pr->clr_reg) {
|
|
fn = REG_FN_WRITE_BASE;
|
|
mode = MODE_PCLR_REG;
|
|
reg_e = pr->set_reg;
|
|
reg_d = pr->clr_reg;
|
|
} else {
|
|
fn = REG_FN_MODIFY_BASE;
|
|
mode = MODE_PRIO_REG;
|
|
if (!pr->set_reg)
|
|
BUG();
|
|
reg_e = pr->set_reg;
|
|
reg_d = pr->set_reg;
|
|
}
|
|
|
|
fn += (pr->reg_width >> 3) - 1;
|
|
n = *fld_idx + 1;
|
|
|
|
BUG_ON(n * pr->field_width > pr->reg_width);
|
|
|
|
bit = pr->reg_width - (n * pr->field_width);
|
|
|
|
return _INTC_MK(fn, mode,
|
|
intc_get_reg(d, reg_e),
|
|
intc_get_reg(d, reg_d),
|
|
pr->field_width, bit);
|
|
}
|
|
|
|
*fld_idx = 0;
|
|
(*reg_idx)++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int __init intc_prio_data(struct intc_desc *desc,
|
|
struct intc_desc_int *d,
|
|
intc_enum enum_id, int do_grps)
|
|
{
|
|
unsigned int i = 0;
|
|
unsigned int j = 0;
|
|
unsigned int ret;
|
|
|
|
ret = _intc_prio_data(desc, d, enum_id, &i, &j);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (do_grps)
|
|
return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __init intc_enable_disable_enum(struct intc_desc *desc,
|
|
struct intc_desc_int *d,
|
|
intc_enum enum_id, int enable)
|
|
{
|
|
unsigned int i, j, data;
|
|
|
|
/* go through and enable/disable all mask bits */
|
|
i = j = 0;
|
|
do {
|
|
data = _intc_mask_data(desc, d, enum_id, &i, &j);
|
|
if (data)
|
|
intc_enable_disable(d, data, enable);
|
|
j++;
|
|
} while (data);
|
|
|
|
/* go through and enable/disable all priority fields */
|
|
i = j = 0;
|
|
do {
|
|
data = _intc_prio_data(desc, d, enum_id, &i, &j);
|
|
if (data)
|
|
intc_enable_disable(d, data, enable);
|
|
|
|
j++;
|
|
} while (data);
|
|
}
|
|
|
|
static unsigned int __init intc_ack_data(struct intc_desc *desc,
|
|
struct intc_desc_int *d,
|
|
intc_enum enum_id)
|
|
{
|
|
struct intc_mask_reg *mr = desc->hw.ack_regs;
|
|
unsigned int i, j, fn, mode;
|
|
unsigned long reg_e, reg_d;
|
|
|
|
for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
|
|
mr = desc->hw.ack_regs + i;
|
|
|
|
for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
|
|
if (mr->enum_ids[j] != enum_id)
|
|
continue;
|
|
|
|
fn = REG_FN_MODIFY_BASE;
|
|
mode = MODE_ENABLE_REG;
|
|
reg_e = mr->set_reg;
|
|
reg_d = mr->set_reg;
|
|
|
|
fn += (mr->reg_width >> 3) - 1;
|
|
return _INTC_MK(fn, mode,
|
|
intc_get_reg(d, reg_e),
|
|
intc_get_reg(d, reg_d),
|
|
1,
|
|
(mr->reg_width - 1) - j);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int __init intc_sense_data(struct intc_desc *desc,
|
|
struct intc_desc_int *d,
|
|
intc_enum enum_id)
|
|
{
|
|
struct intc_sense_reg *sr = desc->hw.sense_regs;
|
|
unsigned int i, j, fn, bit;
|
|
|
|
for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
|
|
sr = desc->hw.sense_regs + i;
|
|
|
|
for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
|
|
if (sr->enum_ids[j] != enum_id)
|
|
continue;
|
|
|
|
fn = REG_FN_MODIFY_BASE;
|
|
fn += (sr->reg_width >> 3) - 1;
|
|
|
|
BUG_ON((j + 1) * sr->field_width > sr->reg_width);
|
|
|
|
bit = sr->reg_width - ((j + 1) * sr->field_width);
|
|
|
|
return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
|
|
0, sr->field_width, bit);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __init intc_register_irq(struct intc_desc *desc,
|
|
struct intc_desc_int *d,
|
|
intc_enum enum_id,
|
|
unsigned int irq)
|
|
{
|
|
struct intc_handle_int *hp;
|
|
unsigned int data[2], primary;
|
|
|
|
/*
|
|
* Register the IRQ position with the global IRQ map
|
|
*/
|
|
set_bit(irq, intc_irq_map);
|
|
|
|
/*
|
|
* Prefer single interrupt source bitmap over other combinations:
|
|
*
|
|
* 1. bitmap, single interrupt source
|
|
* 2. priority, single interrupt source
|
|
* 3. bitmap, multiple interrupt sources (groups)
|
|
* 4. priority, multiple interrupt sources (groups)
|
|
*/
|
|
data[0] = intc_mask_data(desc, d, enum_id, 0);
|
|
data[1] = intc_prio_data(desc, d, enum_id, 0);
|
|
|
|
primary = 0;
|
|
if (!data[0] && data[1])
|
|
primary = 1;
|
|
|
|
if (!data[0] && !data[1])
|
|
pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
|
|
irq, irq2evt(irq));
|
|
|
|
data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
|
|
data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
|
|
|
|
if (!data[primary])
|
|
primary ^= 1;
|
|
|
|
BUG_ON(!data[primary]); /* must have primary masking method */
|
|
|
|
disable_irq_nosync(irq);
|
|
set_irq_chip_and_handler_name(irq, &d->chip,
|
|
handle_level_irq, "level");
|
|
set_irq_chip_data(irq, (void *)data[primary]);
|
|
|
|
/*
|
|
* set priority level
|
|
* - this needs to be at least 2 for 5-bit priorities on 7780
|
|
*/
|
|
intc_prio_level[irq] = default_prio_level;
|
|
|
|
/* enable secondary masking method if present */
|
|
if (data[!primary])
|
|
_intc_enable(irq, data[!primary]);
|
|
|
|
/* add irq to d->prio list if priority is available */
|
|
if (data[1]) {
|
|
hp = d->prio + d->nr_prio;
|
|
hp->irq = irq;
|
|
hp->handle = data[1];
|
|
|
|
if (primary) {
|
|
/*
|
|
* only secondary priority should access registers, so
|
|
* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
|
|
*/
|
|
hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
|
|
hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
|
|
}
|
|
d->nr_prio++;
|
|
}
|
|
|
|
/* add irq to d->sense list if sense is available */
|
|
data[0] = intc_sense_data(desc, d, enum_id);
|
|
if (data[0]) {
|
|
(d->sense + d->nr_sense)->irq = irq;
|
|
(d->sense + d->nr_sense)->handle = data[0];
|
|
d->nr_sense++;
|
|
}
|
|
|
|
/* irq should be disabled by default */
|
|
d->chip.mask(irq);
|
|
|
|
if (desc->hw.ack_regs)
|
|
ack_handle[irq] = intc_ack_data(desc, d, enum_id);
|
|
|
|
#ifdef CONFIG_INTC_BALANCING
|
|
if (desc->hw.mask_regs)
|
|
dist_handle[irq] = intc_dist_data(desc, d, enum_id);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM
|
|
set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
|
|
#endif
|
|
}
|
|
|
|
static unsigned int __init save_reg(struct intc_desc_int *d,
|
|
unsigned int cnt,
|
|
unsigned long value,
|
|
unsigned int smp)
|
|
{
|
|
if (value) {
|
|
value = intc_phys_to_virt(d, value);
|
|
|
|
d->reg[cnt] = value;
|
|
#ifdef CONFIG_SMP
|
|
d->smp[cnt] = smp;
|
|
#endif
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
generic_handle_irq((unsigned int)get_irq_data(irq));
|
|
}
|
|
|
|
int __init register_intc_controller(struct intc_desc *desc)
|
|
{
|
|
unsigned int i, k, smp;
|
|
struct intc_hw_desc *hw = &desc->hw;
|
|
struct intc_desc_int *d;
|
|
struct resource *res;
|
|
|
|
pr_info("Registered controller '%s' with %u IRQs\n",
|
|
desc->name, hw->nr_vectors);
|
|
|
|
d = kzalloc(sizeof(*d), GFP_NOWAIT);
|
|
if (!d)
|
|
goto err0;
|
|
|
|
INIT_LIST_HEAD(&d->list);
|
|
list_add(&d->list, &intc_list);
|
|
|
|
if (desc->num_resources) {
|
|
d->nr_windows = desc->num_resources;
|
|
d->window = kzalloc(d->nr_windows * sizeof(*d->window),
|
|
GFP_NOWAIT);
|
|
if (!d->window)
|
|
goto err1;
|
|
|
|
for (k = 0; k < d->nr_windows; k++) {
|
|
res = desc->resource + k;
|
|
WARN_ON(resource_type(res) != IORESOURCE_MEM);
|
|
d->window[k].phys = res->start;
|
|
d->window[k].size = resource_size(res);
|
|
d->window[k].virt = ioremap_nocache(res->start,
|
|
resource_size(res));
|
|
if (!d->window[k].virt)
|
|
goto err2;
|
|
}
|
|
}
|
|
|
|
d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
|
|
#ifdef CONFIG_INTC_BALANCING
|
|
if (d->nr_reg)
|
|
d->nr_reg += hw->nr_mask_regs;
|
|
#endif
|
|
d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
|
|
d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
|
|
d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
|
|
|
|
d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
|
|
if (!d->reg)
|
|
goto err2;
|
|
|
|
#ifdef CONFIG_SMP
|
|
d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
|
|
if (!d->smp)
|
|
goto err3;
|
|
#endif
|
|
k = 0;
|
|
|
|
if (hw->mask_regs) {
|
|
for (i = 0; i < hw->nr_mask_regs; i++) {
|
|
smp = IS_SMP(hw->mask_regs[i]);
|
|
k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
|
|
k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
|
|
#ifdef CONFIG_INTC_BALANCING
|
|
k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if (hw->prio_regs) {
|
|
d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
|
|
GFP_NOWAIT);
|
|
if (!d->prio)
|
|
goto err4;
|
|
|
|
for (i = 0; i < hw->nr_prio_regs; i++) {
|
|
smp = IS_SMP(hw->prio_regs[i]);
|
|
k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
|
|
k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
|
|
}
|
|
}
|
|
|
|
if (hw->sense_regs) {
|
|
d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
|
|
GFP_NOWAIT);
|
|
if (!d->sense)
|
|
goto err5;
|
|
|
|
for (i = 0; i < hw->nr_sense_regs; i++)
|
|
k += save_reg(d, k, hw->sense_regs[i].reg, 0);
|
|
}
|
|
|
|
d->chip.name = desc->name;
|
|
d->chip.mask = intc_disable;
|
|
d->chip.unmask = intc_enable;
|
|
d->chip.mask_ack = intc_disable;
|
|
d->chip.enable = intc_enable;
|
|
d->chip.disable = intc_disable;
|
|
d->chip.shutdown = intc_disable;
|
|
d->chip.set_type = intc_set_sense;
|
|
d->chip.set_wake = intc_set_wake;
|
|
#ifdef CONFIG_SMP
|
|
d->chip.set_affinity = intc_set_affinity;
|
|
#endif
|
|
|
|
if (hw->ack_regs) {
|
|
for (i = 0; i < hw->nr_ack_regs; i++)
|
|
k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
|
|
|
|
d->chip.mask_ack = intc_mask_ack;
|
|
}
|
|
|
|
/* disable bits matching force_disable before registering irqs */
|
|
if (desc->force_disable)
|
|
intc_enable_disable_enum(desc, d, desc->force_disable, 0);
|
|
|
|
/* disable bits matching force_enable before registering irqs */
|
|
if (desc->force_enable)
|
|
intc_enable_disable_enum(desc, d, desc->force_enable, 0);
|
|
|
|
BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
|
|
|
|
/* register the vectors one by one */
|
|
for (i = 0; i < hw->nr_vectors; i++) {
|
|
struct intc_vect *vect = hw->vectors + i;
|
|
unsigned int irq = evt2irq(vect->vect);
|
|
struct irq_desc *irq_desc;
|
|
|
|
if (!vect->enum_id)
|
|
continue;
|
|
|
|
irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
|
|
if (unlikely(!irq_desc)) {
|
|
pr_err("can't get irq_desc for %d\n", irq);
|
|
continue;
|
|
}
|
|
|
|
intc_register_irq(desc, d, vect->enum_id, irq);
|
|
|
|
for (k = i + 1; k < hw->nr_vectors; k++) {
|
|
struct intc_vect *vect2 = hw->vectors + k;
|
|
unsigned int irq2 = evt2irq(vect2->vect);
|
|
|
|
if (vect->enum_id != vect2->enum_id)
|
|
continue;
|
|
|
|
/*
|
|
* In the case of multi-evt handling and sparse
|
|
* IRQ support, each vector still needs to have
|
|
* its own backing irq_desc.
|
|
*/
|
|
irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
|
|
if (unlikely(!irq_desc)) {
|
|
pr_err("can't get irq_desc for %d\n", irq2);
|
|
continue;
|
|
}
|
|
|
|
vect2->enum_id = 0;
|
|
|
|
/* redirect this interrupts to the first one */
|
|
set_irq_chip(irq2, &dummy_irq_chip);
|
|
set_irq_chained_handler(irq2, intc_redirect_irq);
|
|
set_irq_data(irq2, (void *)irq);
|
|
}
|
|
}
|
|
|
|
/* enable bits matching force_enable after registering irqs */
|
|
if (desc->force_enable)
|
|
intc_enable_disable_enum(desc, d, desc->force_enable, 1);
|
|
|
|
return 0;
|
|
err5:
|
|
kfree(d->prio);
|
|
err4:
|
|
#ifdef CONFIG_SMP
|
|
kfree(d->smp);
|
|
err3:
|
|
#endif
|
|
kfree(d->reg);
|
|
err2:
|
|
for (k = 0; k < d->nr_windows; k++)
|
|
if (d->window[k].virt)
|
|
iounmap(d->window[k].virt);
|
|
|
|
kfree(d->window);
|
|
err1:
|
|
kfree(d);
|
|
err0:
|
|
pr_err("unable to allocate INTC memory\n");
|
|
|
|
return -ENOMEM;
|
|
}
|
|
|
|
#ifdef CONFIG_INTC_USERIMASK
|
|
static void __iomem *uimask;
|
|
|
|
int register_intc_userimask(unsigned long addr)
|
|
{
|
|
if (unlikely(uimask))
|
|
return -EBUSY;
|
|
|
|
uimask = ioremap_nocache(addr, SZ_4K);
|
|
if (unlikely(!uimask))
|
|
return -ENOMEM;
|
|
|
|
pr_info("userimask support registered for levels 0 -> %d\n",
|
|
default_prio_level - 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t
|
|
show_intc_userimask(struct sysdev_class *cls,
|
|
struct sysdev_class_attribute *attr, char *buf)
|
|
{
|
|
return sprintf(buf, "%d\n", (__raw_readl(uimask) >> 4) & 0xf);
|
|
}
|
|
|
|
static ssize_t
|
|
store_intc_userimask(struct sysdev_class *cls,
|
|
struct sysdev_class_attribute *attr,
|
|
const char *buf, size_t count)
|
|
{
|
|
unsigned long level;
|
|
|
|
level = simple_strtoul(buf, NULL, 10);
|
|
|
|
/*
|
|
* Minimal acceptable IRQ levels are in the 2 - 16 range, but
|
|
* these are chomped so as to not interfere with normal IRQs.
|
|
*
|
|
* Level 1 is a special case on some CPUs in that it's not
|
|
* directly settable, but given that USERIMASK cuts off below a
|
|
* certain level, we don't care about this limitation here.
|
|
* Level 0 on the other hand equates to user masking disabled.
|
|
*
|
|
* We use default_prio_level as a cut off so that only special
|
|
* case opt-in IRQs can be mangled.
|
|
*/
|
|
if (level >= default_prio_level)
|
|
return -EINVAL;
|
|
|
|
__raw_writel(0xa5 << 24 | level << 4, uimask);
|
|
|
|
return count;
|
|
}
|
|
|
|
static SYSDEV_CLASS_ATTR(userimask, S_IRUSR | S_IWUSR,
|
|
show_intc_userimask, store_intc_userimask);
|
|
#endif
|
|
|
|
static ssize_t
|
|
show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
|
|
{
|
|
struct intc_desc_int *d;
|
|
|
|
d = container_of(dev, struct intc_desc_int, sysdev);
|
|
|
|
return sprintf(buf, "%s\n", d->chip.name);
|
|
}
|
|
|
|
static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
|
|
|
|
static int intc_suspend(struct sys_device *dev, pm_message_t state)
|
|
{
|
|
struct intc_desc_int *d;
|
|
struct irq_desc *desc;
|
|
int irq;
|
|
|
|
/* get intc controller associated with this sysdev */
|
|
d = container_of(dev, struct intc_desc_int, sysdev);
|
|
|
|
switch (state.event) {
|
|
case PM_EVENT_ON:
|
|
if (d->state.event != PM_EVENT_FREEZE)
|
|
break;
|
|
for_each_irq_desc(irq, desc) {
|
|
if (desc->handle_irq == intc_redirect_irq)
|
|
continue;
|
|
if (desc->chip != &d->chip)
|
|
continue;
|
|
if (desc->status & IRQ_DISABLED)
|
|
intc_disable(irq);
|
|
else
|
|
intc_enable(irq);
|
|
}
|
|
break;
|
|
case PM_EVENT_FREEZE:
|
|
/* nothing has to be done */
|
|
break;
|
|
case PM_EVENT_SUSPEND:
|
|
/* enable wakeup irqs belonging to this intc controller */
|
|
for_each_irq_desc(irq, desc) {
|
|
if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
|
|
intc_enable(irq);
|
|
}
|
|
break;
|
|
}
|
|
d->state = state;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intc_resume(struct sys_device *dev)
|
|
{
|
|
return intc_suspend(dev, PMSG_ON);
|
|
}
|
|
|
|
static struct sysdev_class intc_sysdev_class = {
|
|
.name = "intc",
|
|
.suspend = intc_suspend,
|
|
.resume = intc_resume,
|
|
};
|
|
|
|
/* register this intc as sysdev to allow suspend/resume */
|
|
static int __init register_intc_sysdevs(void)
|
|
{
|
|
struct intc_desc_int *d;
|
|
int error;
|
|
int id = 0;
|
|
|
|
error = sysdev_class_register(&intc_sysdev_class);
|
|
#ifdef CONFIG_INTC_USERIMASK
|
|
if (!error && uimask)
|
|
error = sysdev_class_create_file(&intc_sysdev_class,
|
|
&attr_userimask);
|
|
#endif
|
|
if (!error) {
|
|
list_for_each_entry(d, &intc_list, list) {
|
|
d->sysdev.id = id;
|
|
d->sysdev.cls = &intc_sysdev_class;
|
|
error = sysdev_register(&d->sysdev);
|
|
if (error == 0)
|
|
error = sysdev_create_file(&d->sysdev,
|
|
&attr_name);
|
|
if (error)
|
|
break;
|
|
|
|
id++;
|
|
}
|
|
}
|
|
|
|
if (error)
|
|
pr_err("sysdev registration error\n");
|
|
|
|
return error;
|
|
}
|
|
device_initcall(register_intc_sysdevs);
|
|
|
|
/*
|
|
* Dynamic IRQ allocation and deallocation
|
|
*/
|
|
unsigned int create_irq_nr(unsigned int irq_want, int node)
|
|
{
|
|
unsigned int irq = 0, new;
|
|
unsigned long flags;
|
|
struct irq_desc *desc;
|
|
|
|
spin_lock_irqsave(&vector_lock, flags);
|
|
|
|
/*
|
|
* First try the wanted IRQ
|
|
*/
|
|
if (test_and_set_bit(irq_want, intc_irq_map) == 0) {
|
|
new = irq_want;
|
|
} else {
|
|
/* .. then fall back to scanning. */
|
|
new = find_first_zero_bit(intc_irq_map, nr_irqs);
|
|
if (unlikely(new == nr_irqs))
|
|
goto out_unlock;
|
|
|
|
__set_bit(new, intc_irq_map);
|
|
}
|
|
|
|
desc = irq_to_desc_alloc_node(new, node);
|
|
if (unlikely(!desc)) {
|
|
pr_err("can't get irq_desc for %d\n", new);
|
|
goto out_unlock;
|
|
}
|
|
|
|
desc = move_irq_desc(desc, node);
|
|
irq = new;
|
|
|
|
out_unlock:
|
|
spin_unlock_irqrestore(&vector_lock, flags);
|
|
|
|
if (irq > 0) {
|
|
dynamic_irq_init(irq);
|
|
#ifdef CONFIG_ARM
|
|
set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
|
|
#endif
|
|
}
|
|
|
|
return irq;
|
|
}
|
|
|
|
int create_irq(void)
|
|
{
|
|
int nid = cpu_to_node(smp_processor_id());
|
|
int irq;
|
|
|
|
irq = create_irq_nr(NR_IRQS_LEGACY, nid);
|
|
if (irq == 0)
|
|
irq = -1;
|
|
|
|
return irq;
|
|
}
|
|
|
|
void destroy_irq(unsigned int irq)
|
|
{
|
|
unsigned long flags;
|
|
|
|
dynamic_irq_cleanup(irq);
|
|
|
|
spin_lock_irqsave(&vector_lock, flags);
|
|
__clear_bit(irq, intc_irq_map);
|
|
spin_unlock_irqrestore(&vector_lock, flags);
|
|
}
|
|
|
|
int reserve_irq_vector(unsigned int irq)
|
|
{
|
|
unsigned long flags;
|
|
int ret = 0;
|
|
|
|
spin_lock_irqsave(&vector_lock, flags);
|
|
if (test_and_set_bit(irq, intc_irq_map))
|
|
ret = -EBUSY;
|
|
spin_unlock_irqrestore(&vector_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void reserve_irq_legacy(void)
|
|
{
|
|
unsigned long flags;
|
|
int i, j;
|
|
|
|
spin_lock_irqsave(&vector_lock, flags);
|
|
j = find_first_bit(intc_irq_map, nr_irqs);
|
|
for (i = 0; i < j; i++)
|
|
__set_bit(i, intc_irq_map);
|
|
spin_unlock_irqrestore(&vector_lock, flags);
|
|
}
|