forked from Minki/linux
db7ef289a2
Add readl() and writel() for 'PM_' macros, just like another areas have
done within unicored32, or will cause compiling issue.
The related error (allmodconfig for unicored32):
CC arch/unicore32/kernel/clock.o
arch/unicore32/kernel/clock.c: In function 'clk_set_rate':
arch/unicore32/kernel/clock.c:182: warning: initialization makes integer from pointer without a cast
arch/unicore32/kernel/clock.c:204: error: lvalue required as left operand of assignment
arch/unicore32/kernel/clock.c:206: error: lvalue required as left operand of assignment
arch/unicore32/kernel/clock.c:207: error: invalid operands to binary & (have 'void *' and 'long unsigned int')
make[1]: *** [arch/unicore32/kernel/clock.o] Error 1
make: *** [arch/unicore32/kernel] Error 2
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Acked-by: Xuetao Guan <gxt@mprc.pku.edu.cn>
Signed-off-by: Xuetao Guan <gxt@mprc.pku.edu.cn>
391 lines
10 KiB
C
391 lines
10 KiB
C
/*
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* linux/arch/unicore32/kernel/clock.c
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
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* Copyright (C) 2001-2010 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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/*
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* Very simple clock implementation
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*/
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struct clk {
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struct list_head node;
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unsigned long rate;
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const char *name;
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};
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static struct clk clk_ost_clk = {
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.name = "OST_CLK",
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.rate = CLOCK_TICK_RATE,
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};
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static struct clk clk_mclk_clk = {
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.name = "MAIN_CLK",
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};
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static struct clk clk_bclk32_clk = {
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.name = "BUS32_CLK",
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};
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static struct clk clk_ddr_clk = {
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.name = "DDR_CLK",
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};
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static struct clk clk_vga_clk = {
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.name = "VGA_CLK",
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};
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static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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struct clk *clk_get(struct device *dev, const char *id)
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{
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struct clk *p, *clk = ERR_PTR(-ENOENT);
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mutex_lock(&clocks_mutex);
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list_for_each_entry(p, &clocks, node) {
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if (strcmp(id, p->name) == 0) {
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clk = p;
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break;
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}
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}
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mutex_unlock(&clocks_mutex);
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return clk;
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}
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EXPORT_SYMBOL(clk_get);
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void clk_put(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_put);
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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struct {
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unsigned long rate;
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unsigned long cfg;
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unsigned long div;
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} vga_clk_table[] = {
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{.rate = 25175000, .cfg = 0x00002001, .div = 0x9},
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{.rate = 31500000, .cfg = 0x00002001, .div = 0x7},
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{.rate = 40000000, .cfg = 0x00003801, .div = 0x9},
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{.rate = 49500000, .cfg = 0x00003801, .div = 0x7},
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{.rate = 65000000, .cfg = 0x00002c01, .div = 0x4},
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{.rate = 78750000, .cfg = 0x00002400, .div = 0x7},
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{.rate = 108000000, .cfg = 0x00002c01, .div = 0x2},
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{.rate = 106500000, .cfg = 0x00003c01, .div = 0x3},
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{.rate = 50650000, .cfg = 0x00106400, .div = 0x9},
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{.rate = 61500000, .cfg = 0x00106400, .div = 0xa},
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{.rate = 85500000, .cfg = 0x00002800, .div = 0x6},
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};
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struct {
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unsigned long mrate;
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unsigned long prate;
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} mclk_clk_table[] = {
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{.mrate = 500000000, .prate = 0x00109801},
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{.mrate = 525000000, .prate = 0x00104C00},
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{.mrate = 550000000, .prate = 0x00105000},
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{.mrate = 575000000, .prate = 0x00105400},
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{.mrate = 600000000, .prate = 0x00105800},
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{.mrate = 625000000, .prate = 0x00105C00},
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{.mrate = 650000000, .prate = 0x00106000},
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{.mrate = 675000000, .prate = 0x00106400},
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{.mrate = 700000000, .prate = 0x00106800},
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{.mrate = 725000000, .prate = 0x00106C00},
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{.mrate = 750000000, .prate = 0x00107000},
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{.mrate = 775000000, .prate = 0x00107400},
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{.mrate = 800000000, .prate = 0x00107800},
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};
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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if (clk == &clk_vga_clk) {
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unsigned long pll_vgacfg, pll_vgadiv;
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int ret, i;
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/* lookup vga_clk_table */
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ret = -EINVAL;
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for (i = 0; i < ARRAY_SIZE(vga_clk_table); i++) {
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if (rate == vga_clk_table[i].rate) {
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pll_vgacfg = vga_clk_table[i].cfg;
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pll_vgadiv = vga_clk_table[i].div;
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ret = 0;
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break;
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}
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}
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if (ret)
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return ret;
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if (readl(PM_PLLVGACFG) == pll_vgacfg)
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return 0;
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/* set pll vga cfg reg. */
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writel(pll_vgacfg, PM_PLLVGACFG);
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writel(PM_PMCR_CFBVGA, PM_PMCR);
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while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_VGADFC)
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!= PM_PLLDFCDONE_VGADFC)
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udelay(100); /* about 1ms */
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/* set div cfg reg. */
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writel(readl(PM_PCGR) | PM_PCGR_VGACLK, PM_PCGR);
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writel((readl(PM_DIVCFG) & ~PM_DIVCFG_VGACLK_MASK)
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| PM_DIVCFG_VGACLK(pll_vgadiv), PM_DIVCFG);
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writel(readl(PM_SWRESET) | PM_SWRESET_VGADIV, PM_SWRESET);
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while ((readl(PM_SWRESET) & PM_SWRESET_VGADIV)
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== PM_SWRESET_VGADIV)
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udelay(100); /* 65536 bclk32, about 320us */
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writel(readl(PM_PCGR) & ~PM_PCGR_VGACLK, PM_PCGR);
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}
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#ifdef CONFIG_CPU_FREQ
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if (clk == &clk_mclk_clk) {
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u32 pll_rate, divstatus = readl(PM_DIVSTATUS);
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int ret, i;
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/* lookup mclk_clk_table */
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ret = -EINVAL;
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for (i = 0; i < ARRAY_SIZE(mclk_clk_table); i++) {
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if (rate == mclk_clk_table[i].mrate) {
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pll_rate = mclk_clk_table[i].prate;
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clk_mclk_clk.rate = mclk_clk_table[i].mrate;
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ret = 0;
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break;
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}
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}
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if (ret)
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return ret;
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if (clk_mclk_clk.rate)
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clk_bclk32_clk.rate = clk_mclk_clk.rate
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/ (((divstatus & 0x0000f000) >> 12) + 1);
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/* set pll sys cfg reg. */
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writel(pll_rate, PM_PLLSYSCFG);
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writel(PM_PMCR_CFBSYS, PM_PMCR);
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while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_SYSDFC)
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!= PM_PLLDFCDONE_SYSDFC)
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udelay(100);
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/* about 1ms */
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}
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#endif
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return 0;
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}
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EXPORT_SYMBOL(clk_set_rate);
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int clk_register(struct clk *clk)
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{
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mutex_lock(&clocks_mutex);
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list_add(&clk->node, &clocks);
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mutex_unlock(&clocks_mutex);
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printk(KERN_DEFAULT "PKUnity PM: %s %lu.%02luM\n", clk->name,
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(clk->rate)/1000000, (clk->rate)/10000 % 100);
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return 0;
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}
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EXPORT_SYMBOL(clk_register);
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void clk_unregister(struct clk *clk)
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{
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mutex_lock(&clocks_mutex);
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list_del(&clk->node);
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mutex_unlock(&clocks_mutex);
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}
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EXPORT_SYMBOL(clk_unregister);
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struct {
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unsigned long prate;
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unsigned long rate;
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} pllrate_table[] = {
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{.prate = 0x00002001, .rate = 250000000},
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{.prate = 0x00104801, .rate = 250000000},
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{.prate = 0x00104C01, .rate = 262500000},
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{.prate = 0x00002401, .rate = 275000000},
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{.prate = 0x00105001, .rate = 275000000},
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{.prate = 0x00105401, .rate = 287500000},
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{.prate = 0x00002801, .rate = 300000000},
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{.prate = 0x00105801, .rate = 300000000},
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{.prate = 0x00105C01, .rate = 312500000},
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{.prate = 0x00002C01, .rate = 325000000},
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{.prate = 0x00106001, .rate = 325000000},
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{.prate = 0x00106401, .rate = 337500000},
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{.prate = 0x00003001, .rate = 350000000},
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{.prate = 0x00106801, .rate = 350000000},
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{.prate = 0x00106C01, .rate = 362500000},
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{.prate = 0x00003401, .rate = 375000000},
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{.prate = 0x00107001, .rate = 375000000},
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{.prate = 0x00107401, .rate = 387500000},
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{.prate = 0x00003801, .rate = 400000000},
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{.prate = 0x00107801, .rate = 400000000},
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{.prate = 0x00107C01, .rate = 412500000},
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{.prate = 0x00003C01, .rate = 425000000},
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{.prate = 0x00108001, .rate = 425000000},
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{.prate = 0x00108401, .rate = 437500000},
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{.prate = 0x00004001, .rate = 450000000},
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{.prate = 0x00108801, .rate = 450000000},
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{.prate = 0x00108C01, .rate = 462500000},
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{.prate = 0x00004401, .rate = 475000000},
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{.prate = 0x00109001, .rate = 475000000},
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{.prate = 0x00109401, .rate = 487500000},
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{.prate = 0x00004801, .rate = 500000000},
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{.prate = 0x00109801, .rate = 500000000},
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{.prate = 0x00104C00, .rate = 525000000},
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{.prate = 0x00002400, .rate = 550000000},
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{.prate = 0x00105000, .rate = 550000000},
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{.prate = 0x00105400, .rate = 575000000},
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{.prate = 0x00002800, .rate = 600000000},
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{.prate = 0x00105800, .rate = 600000000},
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{.prate = 0x00105C00, .rate = 625000000},
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{.prate = 0x00002C00, .rate = 650000000},
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{.prate = 0x00106000, .rate = 650000000},
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{.prate = 0x00106400, .rate = 675000000},
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{.prate = 0x00003000, .rate = 700000000},
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{.prate = 0x00106800, .rate = 700000000},
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{.prate = 0x00106C00, .rate = 725000000},
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{.prate = 0x00003400, .rate = 750000000},
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{.prate = 0x00107000, .rate = 750000000},
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{.prate = 0x00107400, .rate = 775000000},
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{.prate = 0x00003800, .rate = 800000000},
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{.prate = 0x00107800, .rate = 800000000},
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{.prate = 0x00107C00, .rate = 825000000},
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{.prate = 0x00003C00, .rate = 850000000},
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{.prate = 0x00108000, .rate = 850000000},
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{.prate = 0x00108400, .rate = 875000000},
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{.prate = 0x00004000, .rate = 900000000},
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{.prate = 0x00108800, .rate = 900000000},
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{.prate = 0x00108C00, .rate = 925000000},
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{.prate = 0x00004400, .rate = 950000000},
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{.prate = 0x00109000, .rate = 950000000},
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{.prate = 0x00109400, .rate = 975000000},
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{.prate = 0x00004800, .rate = 1000000000},
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{.prate = 0x00109800, .rate = 1000000000},
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};
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struct {
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unsigned long prate;
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unsigned long drate;
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} pddr_table[] = {
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{.prate = 0x00100800, .drate = 44236800},
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{.prate = 0x00100C00, .drate = 66355200},
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{.prate = 0x00101000, .drate = 88473600},
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{.prate = 0x00101400, .drate = 110592000},
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{.prate = 0x00101800, .drate = 132710400},
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{.prate = 0x00101C01, .drate = 154828800},
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{.prate = 0x00102001, .drate = 176947200},
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{.prate = 0x00102401, .drate = 199065600},
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{.prate = 0x00102801, .drate = 221184000},
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{.prate = 0x00102C01, .drate = 243302400},
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{.prate = 0x00103001, .drate = 265420800},
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{.prate = 0x00103401, .drate = 287539200},
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{.prate = 0x00103801, .drate = 309657600},
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{.prate = 0x00103C01, .drate = 331776000},
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{.prate = 0x00104001, .drate = 353894400},
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};
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static int __init clk_init(void)
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{
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#ifdef CONFIG_PUV3_PM
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u32 pllrate, divstatus = readl(PM_DIVSTATUS);
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u32 pcgr_val = readl(PM_PCGR);
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int i;
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pcgr_val |= PM_PCGR_BCLKMME | PM_PCGR_BCLKH264E | PM_PCGR_BCLKH264D
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| PM_PCGR_HECLK | PM_PCGR_HDCLK;
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writel(pcgr_val, PM_PCGR);
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pllrate = readl(PM_PLLSYSSTATUS);
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/* lookup pmclk_table */
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clk_mclk_clk.rate = 0;
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for (i = 0; i < ARRAY_SIZE(pllrate_table); i++) {
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if (pllrate == pllrate_table[i].prate) {
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clk_mclk_clk.rate = pllrate_table[i].rate;
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break;
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}
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}
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if (clk_mclk_clk.rate)
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clk_bclk32_clk.rate = clk_mclk_clk.rate /
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(((divstatus & 0x0000f000) >> 12) + 1);
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pllrate = readl(PM_PLLDDRSTATUS);
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/* lookup pddr_table */
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clk_ddr_clk.rate = 0;
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for (i = 0; i < ARRAY_SIZE(pddr_table); i++) {
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if (pllrate == pddr_table[i].prate) {
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clk_ddr_clk.rate = pddr_table[i].drate;
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break;
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}
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}
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pllrate = readl(PM_PLLVGASTATUS);
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/* lookup pvga_table */
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clk_vga_clk.rate = 0;
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for (i = 0; i < ARRAY_SIZE(pllrate_table); i++) {
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if (pllrate == pllrate_table[i].prate) {
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clk_vga_clk.rate = pllrate_table[i].rate;
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break;
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}
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}
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if (clk_vga_clk.rate)
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clk_vga_clk.rate = clk_vga_clk.rate /
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(((divstatus & 0x00f00000) >> 20) + 1);
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clk_register(&clk_vga_clk);
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#endif
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#ifdef CONFIG_ARCH_FPGA
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clk_ddr_clk.rate = 33000000;
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clk_mclk_clk.rate = 33000000;
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clk_bclk32_clk.rate = 33000000;
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#endif
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clk_register(&clk_ddr_clk);
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clk_register(&clk_mclk_clk);
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clk_register(&clk_bclk32_clk);
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clk_register(&clk_ost_clk);
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return 0;
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}
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core_initcall(clk_init);
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