forked from Minki/linux
8190471087
The GT-64111 PCI host bridge has no address translation mechanism, so
it can't generate legacy port accesses. This quirk fixes legacy device
port resources to contain the bus addresses actually generated by the
GT-64111.
I think this is the approach Ben Herrenschmidt suggested long ago:
http://marc.info/?l=linux-kernel&m=119733290624544&w=2
This allows us to remove the IORESOURCE_PCI_FIXED hack from
pcibios_fixup_device_resources(), which converts bus addresses to CPU
addresses. IORESOURCE_PCI_FIXED denotes resources that can't be moved;
it has nothing to do with converting bus to CPU addresses.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Cc: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linux-mips@linux-mips.org
Tested-by: Yoichi Yuasa <yuasa@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/998/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
255 lines
7.6 KiB
C
255 lines
7.6 KiB
C
/*
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* Cobalt Qube/Raq PCI support
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
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* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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#include <asm/gt64120.h>
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#include <cobalt.h>
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#include <irq.h>
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/*
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* PCI slot numbers
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*/
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#define COBALT_PCICONF_CPU 0x06
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#define COBALT_PCICONF_ETH0 0x07
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#define COBALT_PCICONF_RAQSCSI 0x08
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#define COBALT_PCICONF_VIA 0x09
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#define COBALT_PCICONF_PCISLOT 0x0A
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#define COBALT_PCICONF_ETH1 0x0C
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/*
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* The Cobalt board ID information. The boards have an ID number wired
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* into the VIA that is available in the high nibble of register 94.
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*/
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#define VIA_COBALT_BRD_ID_REG 0x94
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#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
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static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
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{
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if (dev->devfn == PCI_DEVFN(0, 0) &&
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(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
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dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
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printk(KERN_INFO "Galileo: fixed bridge class\n");
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}
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
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qube_raq_galileo_early_fixup);
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static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
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struct resource *res)
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{
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struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
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unsigned long offset = hose->io_offset;
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struct resource orig = *res;
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if (!(res->flags & IORESOURCE_IO) ||
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!(res->flags & IORESOURCE_PCI_FIXED))
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return;
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res->start -= offset;
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res->end -= offset;
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dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
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&orig, res);
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}
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static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
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{
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u32 class;
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u8 progif;
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/*
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* If the IDE controller is in legacy mode, pci_setup_device() fills in
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* the resources with the legacy addresses that normally appear on the
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* PCI bus, just as if we had read them from a BAR.
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*
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* However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
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* will never appear on the PCI bus because it converts memory accesses
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* in the PCI I/O region (which is never at address zero) into I/O port
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* accesses with no address translation.
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*
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* For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
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* to physical address 0x100001f0 will become a PCI access to I/O port
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* 0x100001f0. There's no way to generate an access to I/O port 0x1f0,
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* but the VT82C586 IDE controller does respond at 0x100001f0 because
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* it only decodes the low 24 bits of the address.
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*
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* When this quirk runs, the pci_dev resources should contain bus
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* addresses, not Linux I/O port numbers, so convert legacy addresses
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* like 0x1f0 to bus addresses like 0x100001f0. Later, we'll convert
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* them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
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*/
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class = dev->class >> 8;
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if (class != PCI_CLASS_STORAGE_IDE)
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return;
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pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
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if ((progif & 1) == 0) {
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cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
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cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
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}
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if ((progif & 4) == 0) {
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cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
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cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
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cobalt_legacy_ide_fixup);
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static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
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{
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unsigned short cfgword;
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unsigned char lt;
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/* Enable Bus Mastering and fast back to back. */
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pci_read_config_word(dev, PCI_COMMAND, &cfgword);
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cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
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pci_write_config_word(dev, PCI_COMMAND, cfgword);
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/* Enable both ide interfaces. ROM only enables primary one. */
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pci_write_config_byte(dev, 0x40, 0xb);
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/* Set latency timer to reasonable value. */
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
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if (lt < 64)
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
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qube_raq_via_bmIDE_fixup);
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static void qube_raq_galileo_fixup(struct pci_dev *dev)
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{
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if (dev->devfn != PCI_DEVFN(0, 0))
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return;
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/* Fix PCI latency-timer and cache-line-size values in Galileo
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* host bridge.
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*/
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
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/*
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* The code described by the comment below has been removed
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* as it causes bus mastering by the Ethernet controllers
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* to break under any kind of network load. We always set
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* the retry timeouts to their maximum.
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*
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* --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
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*
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* On all machines prior to Q2, we had the STOP line disconnected
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* from Galileo to VIA on PCI. The new Galileo does not function
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* correctly unless we have it connected.
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*
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* Therefore we must set the disconnect/retry cycle values to
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* something sensible when using the new Galileo.
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*/
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printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
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#if 0
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if (dev->revision >= 0x10) {
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/* New Galileo, assumes PCI stop line to VIA is connected. */
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GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
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} else if (dev->revision == 0x1 || dev->revision == 0x2)
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#endif
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{
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signed int timeo;
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/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
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timeo = GT_READ(GT_PCI0_TOR_OFS);
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/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
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GT_WRITE(GT_PCI0_TOR_OFS,
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(0xff << 16) | /* retry count */
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(0xff << 8) | /* timeout 1 */
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0xff); /* timeout 0 */
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/* enable PCI retry exceeded interrupt */
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GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
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qube_raq_galileo_fixup);
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int cobalt_board_id;
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static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
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{
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u8 id;
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int retval;
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retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
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if (retval) {
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panic("Cannot read board ID");
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return;
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}
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cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
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printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
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qube_raq_via_board_id_fixup);
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static char irq_tab_qube1[] __initdata = {
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[COBALT_PCICONF_CPU] = 0,
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[COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
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[COBALT_PCICONF_VIA] = 0,
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[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
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[COBALT_PCICONF_ETH1] = 0
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};
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static char irq_tab_cobalt[] __initdata = {
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[COBALT_PCICONF_CPU] = 0,
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[COBALT_PCICONF_ETH0] = ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
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[COBALT_PCICONF_VIA] = 0,
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[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
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[COBALT_PCICONF_ETH1] = ETH1_IRQ
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};
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static char irq_tab_raq2[] __initdata = {
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[COBALT_PCICONF_CPU] = 0,
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[COBALT_PCICONF_ETH0] = ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
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[COBALT_PCICONF_VIA] = 0,
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[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
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[COBALT_PCICONF_ETH1] = ETH1_IRQ
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};
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
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return irq_tab_qube1[slot];
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if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
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return irq_tab_raq2[slot];
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return irq_tab_cobalt[slot];
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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