9352b05b6e
Many V6 and V7 platforms have an L2x0 cache, so make CONFIG_MIGHT_HAVE_CACHE_L2X0 visible for V6 and V7 multi-platform builds. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
45 lines
882 B
Plaintext
45 lines
882 B
Plaintext
config ARCH_SIRF
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bool "CSR SiRF" if ARCH_MULTI_V7
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_IRQ_CHIP
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select NO_IOPORT
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select PINCTRL
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select PINCTRL_SIRF
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help
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Support for CSR SiRFprimaII/Marco/Polo platforms
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if ARCH_SIRF
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menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
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config ARCH_ATLAS6
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bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
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default y
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select SIRF_IRQ
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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config ARCH_PRIMA2
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bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
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default y
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select SIRF_IRQ
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select ZONE_DMA
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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config ARCH_MARCO
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bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
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default y
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select ARM_GIC
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select HAVE_ARM_SCU if SMP
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select SMP_ON_UP if SMP
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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endmenu
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config SIRF_IRQ
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bool
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endif
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