forked from Minki/linux
8f5ec0a57e
Add IRQC interrupt controller support to r8a7790 by hooking up a single IRQC instances to handle 4 external IRQ signals. The IRQC controller is tied to SPIs of the GIC. On r8a7790 the external IRQ pins routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
64 lines
1.3 KiB
Plaintext
64 lines
1.3 KiB
Plaintext
/*
|
|
* Device Tree Source for the r8a7790 SoC
|
|
*
|
|
* Copyright (C) 2013 Renesas Solutions Corp.
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public License
|
|
* version 2. This program is licensed "as is" without any warranty of any
|
|
* kind, whether express or implied.
|
|
*/
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "renesas,r8a7790";
|
|
interrupt-parent = <&gic>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0>;
|
|
clock-frequency = <1300000000>;
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@f1001000 {
|
|
compatible = "arm,cortex-a15-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0xf1001000 0x1000>,
|
|
<0xf1002000 0x1000>,
|
|
<0xf1004000 0x2000>,
|
|
<0xf1006000 0x2000>;
|
|
interrupts = <1 9 0xf04>;
|
|
|
|
gic-cpuif@4 {
|
|
compatible = "arm,gic-cpuif";
|
|
cpuif-id = <4>;
|
|
cpu = <&cpu0>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <1 13 0xf08>,
|
|
<1 14 0xf08>,
|
|
<1 11 0xf08>,
|
|
<1 10 0xf08>;
|
|
};
|
|
|
|
irqc0: interrupt-controller@e61c0000 {
|
|
compatible = "renesas,irqc";
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
reg = <0xe61c0000 0x200>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
|
|
};
|
|
};
|