forked from Minki/linux
4c2880b31c
Commit 3228950621 ("irqchip: gic: Preserve gic V2 bypass bits in cpu
ctrl register") added a new function, gic_cpu_if_up(), to program the
GIC CPU_CTRL register. This function assumes that there is only one GIC
instance present and hence always uses the chip data for the primary GIC
controller. Although it is not common for there to be a secondary, some
devices do support a secondary. Therefore, fix this by passing
gic_cpu_if_up() a pointer to the appropriate chip data structure.
Similarly, the function gic_cpu_if_down() only assumes that there is a
single GIC instance present. Update this function so that an instance
number is passed for the appropriate GIC and return an error code on
failure. The vexpress TC2 (which has a single GIC) is currently the only
user of this function and so update it accordingly. Note that because the
TC2 only has a single GIC, the call to gic_cpu_if_down() should always
be successful.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1438332252-25248-2-git-send-email-jonathanh@nvidia.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
267 lines
7.3 KiB
C
267 lines
7.3 KiB
C
/*
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* arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
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*
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* Created by: Nicolas Pitre, October 2012
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* Copyright: (C) 2012-2013 Linaro Limited
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*
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* Some portions of this file were originally written by Achin Gupta
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* Copyright: (C) 2012 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/errno.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/mcpm.h>
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#include <asm/proc-fns.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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#include <linux/arm-cci.h>
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#include "spc.h"
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/* SCC conf registers */
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#define RESET_CTRL 0x018
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#define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu)))
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#define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu)))
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#define A15_CONF 0x400
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#define A7_CONF 0x500
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#define SYS_INFO 0x700
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#define SPC_BASE 0xb00
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static void __iomem *scc;
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#define TC2_CLUSTERS 2
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#define TC2_MAX_CPUS_PER_CLUSTER 3
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static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
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static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster)
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{
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
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return -EINVAL;
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ve_spc_set_resume_addr(cluster, cpu,
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virt_to_phys(mcpm_entry_point));
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ve_spc_cpu_wakeup_irq(cluster, cpu, true);
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return 0;
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}
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static int tc2_pm_cluster_powerup(unsigned int cluster)
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{
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pr_debug("%s: cluster %u\n", __func__, cluster);
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if (cluster >= TC2_CLUSTERS)
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return -EINVAL;
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ve_spc_powerdown(cluster, false);
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return 0;
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}
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static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
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{
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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ve_spc_cpu_wakeup_irq(cluster, cpu, true);
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/*
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* If the CPU is committed to power down, make sure
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* the power controller will be in charge of waking it
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* up upon IRQ, ie IRQ lines are cut from GIC CPU IF
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* to the CPU by disabling the GIC CPU IF to prevent wfi
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* from completing execution behind power controller back
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*/
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gic_cpu_if_down(0);
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}
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static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster)
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{
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pr_debug("%s: cluster %u\n", __func__, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS);
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ve_spc_powerdown(cluster, true);
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ve_spc_global_wakeup_irq(true);
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}
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static void tc2_pm_cpu_cache_disable(void)
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{
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v7_exit_coherency_flush(louis);
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}
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static void tc2_pm_cluster_cache_disable(void)
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{
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
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/*
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* On the Cortex-A15 we need to disable
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* L2 prefetching before flushing the cache.
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*/
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asm volatile(
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"mcr p15, 1, %0, c15, c0, 3 \n\t"
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"isb \n\t"
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"dsb "
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: : "r" (0x400) );
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}
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v7_exit_coherency_flush(all);
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cci_disable_port_by_cpu(read_cpuid_mpidr());
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}
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static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster)
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{
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u32 mask = cluster ?
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RESET_A7_NCORERESET(cpu)
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: RESET_A15_NCORERESET(cpu);
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return !(readl_relaxed(scc + RESET_CTRL) & mask);
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}
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#define POLL_MSEC 10
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#define TIMEOUT_MSEC 1000
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static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
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{
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unsigned tries;
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) {
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pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n",
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__func__, cpu, cluster,
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readl_relaxed(scc + RESET_CTRL));
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/*
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* We need the CPU to reach WFI, but the power
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* controller may put the cluster in reset and
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* power it off as soon as that happens, before
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* we have a chance to see STANDBYWFI.
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*
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* So we need to check for both conditions:
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*/
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if (tc2_core_in_reset(cpu, cluster) ||
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ve_spc_cpu_in_wfi(cpu, cluster))
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return 0; /* success: the CPU is halted */
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/* Otherwise, wait and retry: */
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msleep(POLL_MSEC);
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}
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return -ETIMEDOUT; /* timeout */
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}
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static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster)
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{
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ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
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}
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static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster)
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{
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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ve_spc_cpu_wakeup_irq(cluster, cpu, false);
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ve_spc_set_resume_addr(cluster, cpu, 0);
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}
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static void tc2_pm_cluster_is_up(unsigned int cluster)
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{
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pr_debug("%s: cluster %u\n", __func__, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS);
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ve_spc_powerdown(cluster, false);
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ve_spc_global_wakeup_irq(false);
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}
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static const struct mcpm_platform_ops tc2_pm_power_ops = {
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.cpu_powerup = tc2_pm_cpu_powerup,
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.cluster_powerup = tc2_pm_cluster_powerup,
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.cpu_suspend_prepare = tc2_pm_cpu_suspend_prepare,
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.cpu_powerdown_prepare = tc2_pm_cpu_powerdown_prepare,
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.cluster_powerdown_prepare = tc2_pm_cluster_powerdown_prepare,
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.cpu_cache_disable = tc2_pm_cpu_cache_disable,
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.cluster_cache_disable = tc2_pm_cluster_cache_disable,
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.wait_for_powerdown = tc2_pm_wait_for_powerdown,
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.cpu_is_up = tc2_pm_cpu_is_up,
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.cluster_is_up = tc2_pm_cluster_is_up,
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};
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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*/
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static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
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{
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asm volatile (" \n"
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" cmp r0, #1 \n"
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" bxne lr \n"
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" b cci_enable_port_for_self ");
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}
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static int __init tc2_pm_init(void)
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{
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unsigned int mpidr, cpu, cluster;
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int ret, irq;
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u32 a15_cluster_id, a7_cluster_id, sys_info;
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struct device_node *np;
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/*
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* The power management-related features are hidden behind
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* SCC registers. We need to extract runtime information like
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* cluster ids and number of CPUs really available in clusters.
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*/
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np = of_find_compatible_node(NULL, NULL,
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"arm,vexpress-scc,v2p-ca15_a7");
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scc = of_iomap(np, 0);
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if (!scc)
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return -ENODEV;
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a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf;
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a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf;
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if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS)
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return -EINVAL;
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sys_info = readl_relaxed(scc + SYS_INFO);
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tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf;
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tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf;
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irq = irq_of_parse_and_map(np, 0);
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/*
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* A subset of the SCC registers is also used to communicate
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* with the SPC (power controller). We need to be able to
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* drive it very early in the boot process to power up
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* processors, so we initialize the SPC driver here.
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*/
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ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id, irq);
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if (ret)
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return ret;
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if (!cci_probed())
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return -ENODEV;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
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pr_err("%s: boot CPU is out of bound!\n", __func__);
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return -EINVAL;
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}
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ret = mcpm_platform_register(&tc2_pm_power_ops);
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if (!ret) {
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mcpm_sync_init(tc2_pm_power_up_setup);
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/* test if we can (re)enable the CCI on our own */
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BUG_ON(mcpm_loopback(tc2_pm_cluster_cache_disable) != 0);
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pr_info("TC2 power management initialized\n");
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}
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return ret;
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}
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early_initcall(tc2_pm_init);
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