David S. Miller 8c79bfa511 sparc64: Add hypervisor interfaces for SPARC-T4 perf counter access. ... Unlike for previous chips, access to the perf-counter control registers are all hyper-privileged. Therefore, access to them must go through a hypervisor interface. Signed-off-by: David S. Miller <davem@davemloft.net>		2012-08-18 23:03:53 -07:00
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asm	sparc64: Add hypervisor interfaces for SPARC-T4 perf counter access.	2012-08-18 23:03:53 -07:00