forked from Minki/linux
8c3583b634
instead of reading the registers everytime the current implementation respect the following constrain: - allow 1 to n soc to be enabled - allow to have a virtual cpu type and subtype - always detect the cpu type and subtype and report it - detect if the soc support is enabled - prepare for sysfs export support - drop soc specific code via compiler when the soc not enabled (via cpu_is_xxx) Today if we read the exid we will have the same value for 9g35 and 9m11 and we will need to check the cidr too with the new implementation we just need to check the soc subtype this will also allow to have specific virtual subtype for rm9200 which the board will have to specify via at91rm9200_set_type(int) as we have no way to detect it. this implementation is inspired by the SH cpu detection support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
366 lines
8.7 KiB
C
366 lines
8.7 KiB
C
/*
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* arch/arm/mach-at91/at91sam9rl.c
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*
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* Copyright (C) 2005 SAN People
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* Copyright (C) 2007 Atmel Corporation
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/cpu.h>
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#include <mach/at91_dbgu.h>
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#include <mach/at91sam9rl.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_rstc.h>
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#include <mach/at91_shdwc.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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static struct map_desc at91sam9rl_sram_desc[] __initdata = {
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{
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.pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
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.type = MT_DEVICE,
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}
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};
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioD_clk = {
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.name = "pioD_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi_clk = {
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.name = "spi_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_SPI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc0_clk = {
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.name = "tc0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc1_clk = {
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.name = "tc1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc2_clk = {
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.name = "tc2_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tsc_clk = {
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.name = "tsc_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udphs_clk = {
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.name = "udphs_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ac97_clk = {
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.name = "ac97_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&pioD_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&mmc_clk,
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&twi0_clk,
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&twi1_clk,
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&spi_clk,
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&ssc0_clk,
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&ssc1_clk,
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&tc0_clk,
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&tc1_clk,
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&tc2_clk,
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&pwm_clk,
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&tsc_clk,
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&dma_clk,
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&udphs_clk,
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&lcdc_clk,
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&ac97_clk,
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// irq0
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
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CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9rl_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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clk_register(&pck0);
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clk_register(&pck1);
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}
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static struct clk_lookup console_clock_lookup;
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void __init at91sam9rl_set_console_clock(int id)
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{
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if (id >= ARRAY_SIZE(usart_clocks_lookups))
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return;
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console_clock_lookup.con_id = "usart";
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console_clock_lookup.clk = usart_clocks_lookups[id].clk;
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clkdev_add(&console_clock_lookup);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9rl_gpio[] = {
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{
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.id = AT91SAM9RL_ID_PIOA,
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.offset = AT91_PIOA,
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.clock = &pioA_clk,
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}, {
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.id = AT91SAM9RL_ID_PIOB,
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.offset = AT91_PIOB,
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.clock = &pioB_clk,
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}, {
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.id = AT91SAM9RL_ID_PIOC,
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.offset = AT91_PIOC,
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.clock = &pioC_clk,
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}, {
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.id = AT91SAM9RL_ID_PIOD,
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.offset = AT91_PIOD,
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.clock = &pioD_clk,
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}
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};
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static void at91sam9rl_poweroff(void)
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{
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at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
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}
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/* --------------------------------------------------------------------
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* AT91SAM9RL processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9rl_map_io(void)
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{
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unsigned long sram_size;
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switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
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case AT91_CIDR_SRAMSIZ_32K:
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sram_size = 2 * SZ_16K;
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break;
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case AT91_CIDR_SRAMSIZ_16K:
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default:
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sram_size = SZ_16K;
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}
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at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
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at91sam9rl_sram_desc->length = sram_size;
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/* Map SRAM */
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iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
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}
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static void __init at91sam9rl_initialize(unsigned long main_clock)
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{
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at91_arch_reset = at91sam9_alt_reset;
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pm_power_off = at91sam9rl_poweroff;
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at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
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/* Init clock subsystem */
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at91_clock_init(main_clock);
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/* Register the processor-specific clocks */
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at91sam9rl_register_clocks();
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9rl_gpio, 4);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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1, /* Parallel IO Controller D */
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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5, /* USART 3 */
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0, /* Multimedia Card Interface */
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6, /* Two-Wire Interface 0 */
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6, /* Two-Wire Interface 1 */
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5, /* Serial Peripheral Interface */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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0, /* Timer Counter 0 */
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0, /* Timer Counter 1 */
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0, /* Timer Counter 2 */
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0,
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0, /* Touch Screen Controller */
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0, /* DMA Controller */
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2, /* USB Device High speed port */
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2, /* LCD Controller */
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6, /* AC97 Controller */
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0,
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0,
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0,
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0,
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0,
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0,
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0, /* Advanced Interrupt Controller */
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};
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struct at91_init_soc __initdata at91sam9rl_soc = {
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.map_io = at91sam9rl_map_io,
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.default_irq_priority = at91sam9rl_default_irq_priority,
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.init = at91sam9rl_initialize,
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};
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