Christoffer Dall 8bf9a701e1 arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs ... The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. We currently simulate this behavior by writing a hardcoded value to the register for the SGIs and PPIs on every write of these bits to the register (ignoring what the guest actually wrote), and by writing the same value as the reset value to the register. This is a bit counter-intuitive, as the register is RO for these bits, and we can just implement it that way, allowing us to control the value of the bits purely in the reset code. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>		2015-10-22 23:01:42 +02:00
..
kvm	arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs	2015-10-22 23:01:42 +02:00