forked from Minki/linux
1638 lines
45 KiB
C
1638 lines
45 KiB
C
/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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*/
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/*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#define MAX_NOPID ((u32)~0)
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/**
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* Interrupts that are always left unmasked.
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*
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* Since pipe events are edge-triggered from the PIPESTAT register to IIR,
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* we leave them always unmasked in IMR and then control enabling them through
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* PIPESTAT alone.
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*/
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#define I915_INTERRUPT_ENABLE_FIX \
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(I915_ASLE_INTERRUPT | \
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
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I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
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/** Interrupts that we mask and unmask at runtime. */
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#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
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#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
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PIPE_VBLANK_INTERRUPT_STATUS)
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#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
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PIPE_VBLANK_INTERRUPT_ENABLE)
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#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
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DRM_I915_VBLANK_PIPE_B)
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void
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ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
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dev_priv->gt_irq_mask_reg &= ~mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
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(void) I915_READ(GTIMR);
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}
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}
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void
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ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
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dev_priv->gt_irq_mask_reg |= mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
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(void) I915_READ(GTIMR);
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}
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}
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/* For display hotplug interrupt */
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static void
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ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask_reg & mask) != 0) {
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dev_priv->irq_mask_reg &= ~mask;
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I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
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(void) I915_READ(DEIMR);
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}
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}
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static inline void
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ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask_reg & mask) != mask) {
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dev_priv->irq_mask_reg |= mask;
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I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
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(void) I915_READ(DEIMR);
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}
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}
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void
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i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask_reg & mask) != 0) {
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dev_priv->irq_mask_reg &= ~mask;
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I915_WRITE(IMR, dev_priv->irq_mask_reg);
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(void) I915_READ(IMR);
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}
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}
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void
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i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask_reg & mask) != mask) {
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dev_priv->irq_mask_reg |= mask;
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I915_WRITE(IMR, dev_priv->irq_mask_reg);
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(void) I915_READ(IMR);
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}
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}
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static inline u32
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i915_pipestat(int pipe)
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{
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if (pipe == 0)
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return PIPEASTAT;
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if (pipe == 1)
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return PIPEBSTAT;
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BUG();
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}
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void
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i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
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{
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if ((dev_priv->pipestat[pipe] & mask) != mask) {
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u32 reg = i915_pipestat(pipe);
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dev_priv->pipestat[pipe] |= mask;
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/* Enable the interrupt, clear any pending status */
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I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
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(void) I915_READ(reg);
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}
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}
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void
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i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
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{
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if ((dev_priv->pipestat[pipe] & mask) != 0) {
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u32 reg = i915_pipestat(pipe);
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dev_priv->pipestat[pipe] &= ~mask;
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I915_WRITE(reg, dev_priv->pipestat[pipe]);
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(void) I915_READ(reg);
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}
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}
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/**
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* intel_enable_asle - enable ASLE interrupt for OpRegion
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*/
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void intel_enable_asle (struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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if (HAS_PCH_SPLIT(dev))
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ironlake_enable_display_irq(dev_priv, DE_GSE);
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else {
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i915_enable_pipestat(dev_priv, 1,
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PIPE_LEGACY_BLC_EVENT_ENABLE);
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if (INTEL_INFO(dev)->gen >= 4)
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i915_enable_pipestat(dev_priv, 0,
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PIPE_LEGACY_BLC_EVENT_ENABLE);
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}
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}
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/**
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* i915_pipe_enabled - check if a pipe is enabled
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* @dev: DRM device
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* @pipe: pipe to check
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*
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* Reading certain registers when the pipe is disabled can hang the chip.
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* Use this routine to make sure the PLL is running and the pipe is active
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* before reading such registers if unsure.
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*/
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static int
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i915_pipe_enabled(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
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}
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/* Called from drm generic code, passed a 'crtc', which
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* we use as a pipe index
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*/
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u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long high_frame;
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unsigned long low_frame;
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u32 high1, high2, low;
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if (!i915_pipe_enabled(dev, pipe)) {
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DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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"pipe %d\n", pipe);
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return 0;
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}
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high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
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low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
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/*
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* High & low register fields aren't synchronized, so make sure
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* we get a low value that's stable across two reads of the high
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* register.
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*/
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do {
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high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
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low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
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high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
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} while (high1 != high2);
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high1 >>= PIPE_FRAME_HIGH_SHIFT;
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low >>= PIPE_FRAME_LOW_SHIFT;
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return (high1 << 8) | low;
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}
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u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
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if (!i915_pipe_enabled(dev, pipe)) {
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DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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"pipe %d\n", pipe);
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return 0;
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}
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return I915_READ(reg);
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}
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/*
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* Handle hotplug events outside the interrupt handler proper.
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*/
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static void i915_hotplug_work_func(struct work_struct *work)
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{
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drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
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hotplug_work);
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struct drm_device *dev = dev_priv->dev;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct intel_encoder *encoder;
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list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
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if (encoder->hot_plug)
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encoder->hot_plug(encoder);
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/* Just fire off a uevent and let userspace tell us what to do */
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drm_helper_hpd_irq_event(dev);
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}
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static void i915_handle_rps_change(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 busy_up, busy_down, max_avg, min_avg;
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u8 new_delay = dev_priv->cur_delay;
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I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
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busy_up = I915_READ(RCPREVBSYTUPAVG);
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busy_down = I915_READ(RCPREVBSYTDNAVG);
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max_avg = I915_READ(RCBMAXAVG);
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min_avg = I915_READ(RCBMINAVG);
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/* Handle RCS change request from hw */
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if (busy_up > max_avg) {
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if (dev_priv->cur_delay != dev_priv->max_delay)
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new_delay = dev_priv->cur_delay - 1;
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if (new_delay < dev_priv->max_delay)
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new_delay = dev_priv->max_delay;
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} else if (busy_down < min_avg) {
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if (dev_priv->cur_delay != dev_priv->min_delay)
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new_delay = dev_priv->cur_delay + 1;
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if (new_delay > dev_priv->min_delay)
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new_delay = dev_priv->min_delay;
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}
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if (ironlake_set_drps(dev, new_delay))
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dev_priv->cur_delay = new_delay;
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return;
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}
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static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int ret = IRQ_NONE;
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u32 de_iir, gt_iir, de_ier, pch_iir;
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struct drm_i915_master_private *master_priv;
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struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
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u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
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if (IS_GEN6(dev))
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bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
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/* disable master interrupt before clearing iir */
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de_ier = I915_READ(DEIER);
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I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
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(void)I915_READ(DEIER);
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de_iir = I915_READ(DEIIR);
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gt_iir = I915_READ(GTIIR);
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pch_iir = I915_READ(SDEIIR);
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if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
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goto done;
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ret = IRQ_HANDLED;
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if (dev->primary->master) {
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master_priv = dev->primary->master->driver_priv;
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if (master_priv->sarea_priv)
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master_priv->sarea_priv->last_dispatch =
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READ_BREADCRUMB(dev_priv);
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}
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if (gt_iir & GT_PIPE_NOTIFY) {
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u32 seqno = render_ring->get_seqno(dev, render_ring);
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render_ring->irq_gem_seqno = seqno;
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trace_i915_gem_request_complete(dev, seqno);
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wake_up_all(&dev_priv->render_ring.irq_queue);
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dev_priv->hangcheck_count = 0;
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mod_timer(&dev_priv->hangcheck_timer,
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jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
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}
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if (gt_iir & bsd_usr_interrupt)
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wake_up_all(&dev_priv->bsd_ring.irq_queue);
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if (de_iir & DE_GSE)
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intel_opregion_gse_intr(dev);
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if (de_iir & DE_PLANEA_FLIP_DONE) {
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intel_prepare_page_flip(dev, 0);
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intel_finish_page_flip_plane(dev, 0);
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}
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if (de_iir & DE_PLANEB_FLIP_DONE) {
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intel_prepare_page_flip(dev, 1);
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intel_finish_page_flip_plane(dev, 1);
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}
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if (de_iir & DE_PIPEA_VBLANK)
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drm_handle_vblank(dev, 0);
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if (de_iir & DE_PIPEB_VBLANK)
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drm_handle_vblank(dev, 1);
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/* check event from PCH */
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if ((de_iir & DE_PCH_EVENT) &&
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(pch_iir & SDE_HOTPLUG_MASK)) {
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queue_work(dev_priv->wq, &dev_priv->hotplug_work);
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}
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if (de_iir & DE_PCU_EVENT) {
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I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
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i915_handle_rps_change(dev);
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}
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/* should clear PCH hotplug event before clear CPU irq */
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I915_WRITE(SDEIIR, pch_iir);
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I915_WRITE(GTIIR, gt_iir);
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I915_WRITE(DEIIR, de_iir);
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done:
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I915_WRITE(DEIER, de_ier);
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(void)I915_READ(DEIER);
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return ret;
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}
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/**
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* i915_error_work_func - do process context error handling work
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* @work: work struct
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*
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* Fire an error uevent so userspace can see that a hang or error
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* was detected.
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*/
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static void i915_error_work_func(struct work_struct *work)
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{
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drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
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error_work);
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struct drm_device *dev = dev_priv->dev;
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char *error_event[] = { "ERROR=1", NULL };
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char *reset_event[] = { "RESET=1", NULL };
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char *reset_done_event[] = { "ERROR=0", NULL };
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kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
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if (atomic_read(&dev_priv->mm.wedged)) {
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DRM_DEBUG_DRIVER("resetting chip\n");
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kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
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if (!i915_reset(dev, GRDOM_RENDER)) {
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atomic_set(&dev_priv->mm.wedged, 0);
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kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
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}
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complete_all(&dev_priv->error_completion);
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}
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}
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|
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#ifdef CONFIG_DEBUG_FS
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static struct drm_i915_error_object *
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i915_error_object_create(struct drm_device *dev,
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struct drm_gem_object *src)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_error_object *dst;
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struct drm_i915_gem_object *src_priv;
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int page, page_count;
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u32 reloc_offset;
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|
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if (src == NULL)
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return NULL;
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|
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src_priv = to_intel_bo(src);
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if (src_priv->pages == NULL)
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return NULL;
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page_count = src->size / PAGE_SIZE;
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dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
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if (dst == NULL)
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return NULL;
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|
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reloc_offset = src_priv->gtt_offset;
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for (page = 0; page < page_count; page++) {
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unsigned long flags;
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void __iomem *s;
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void *d;
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d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
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if (d == NULL)
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goto unwind;
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local_irq_save(flags);
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s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
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reloc_offset,
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KM_IRQ0);
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memcpy_fromio(d, s, PAGE_SIZE);
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io_mapping_unmap_atomic(s, KM_IRQ0);
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local_irq_restore(flags);
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dst->pages[page] = d;
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reloc_offset += PAGE_SIZE;
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}
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dst->page_count = page_count;
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dst->gtt_offset = src_priv->gtt_offset;
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return dst;
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unwind:
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while (page--)
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kfree(dst->pages[page]);
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kfree(dst);
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return NULL;
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}
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|
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static void
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i915_error_object_free(struct drm_i915_error_object *obj)
|
|
{
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int page;
|
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|
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if (obj == NULL)
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return;
|
|
|
|
for (page = 0; page < obj->page_count; page++)
|
|
kfree(obj->pages[page]);
|
|
|
|
kfree(obj);
|
|
}
|
|
|
|
static void
|
|
i915_error_state_free(struct drm_device *dev,
|
|
struct drm_i915_error_state *error)
|
|
{
|
|
i915_error_object_free(error->batchbuffer[0]);
|
|
i915_error_object_free(error->batchbuffer[1]);
|
|
i915_error_object_free(error->ringbuffer);
|
|
kfree(error->active_bo);
|
|
kfree(error->overlay);
|
|
kfree(error);
|
|
}
|
|
|
|
static u32
|
|
i915_get_bbaddr(struct drm_device *dev, u32 *ring)
|
|
{
|
|
u32 cmd;
|
|
|
|
if (IS_I830(dev) || IS_845G(dev))
|
|
cmd = MI_BATCH_BUFFER;
|
|
else if (INTEL_INFO(dev)->gen >= 4)
|
|
cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
|
|
MI_BATCH_NON_SECURE_I965);
|
|
else
|
|
cmd = (MI_BATCH_BUFFER_START | (2 << 6));
|
|
|
|
return ring[0] == cmd ? ring[1] : 0;
|
|
}
|
|
|
|
static u32
|
|
i915_ringbuffer_last_batch(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
u32 head, bbaddr;
|
|
u32 *ring;
|
|
|
|
/* Locate the current position in the ringbuffer and walk back
|
|
* to find the most recently dispatched batch buffer.
|
|
*/
|
|
bbaddr = 0;
|
|
head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
|
|
ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
|
|
|
|
while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
|
|
bbaddr = i915_get_bbaddr(dev, ring);
|
|
if (bbaddr)
|
|
break;
|
|
}
|
|
|
|
if (bbaddr == 0) {
|
|
ring = (u32 *)(dev_priv->render_ring.virtual_start
|
|
+ dev_priv->render_ring.size);
|
|
while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
|
|
bbaddr = i915_get_bbaddr(dev, ring);
|
|
if (bbaddr)
|
|
break;
|
|
}
|
|
}
|
|
|
|
return bbaddr;
|
|
}
|
|
|
|
/**
|
|
* i915_capture_error_state - capture an error record for later analysis
|
|
* @dev: drm device
|
|
*
|
|
* Should be called when an error is detected (either a hang or an error
|
|
* interrupt) to capture error state from the time of the error. Fills
|
|
* out a structure which becomes available in debugfs for user level tools
|
|
* to pick up.
|
|
*/
|
|
static void i915_capture_error_state(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_i915_gem_object *obj_priv;
|
|
struct drm_i915_error_state *error;
|
|
struct drm_gem_object *batchbuffer[2];
|
|
unsigned long flags;
|
|
u32 bbaddr;
|
|
int count;
|
|
|
|
spin_lock_irqsave(&dev_priv->error_lock, flags);
|
|
error = dev_priv->first_error;
|
|
spin_unlock_irqrestore(&dev_priv->error_lock, flags);
|
|
if (error)
|
|
return;
|
|
|
|
error = kmalloc(sizeof(*error), GFP_ATOMIC);
|
|
if (!error) {
|
|
DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
|
|
return;
|
|
}
|
|
|
|
DRM_DEBUG_DRIVER("generating error event\n");
|
|
|
|
error->seqno =
|
|
dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring);
|
|
error->eir = I915_READ(EIR);
|
|
error->pgtbl_er = I915_READ(PGTBL_ER);
|
|
error->pipeastat = I915_READ(PIPEASTAT);
|
|
error->pipebstat = I915_READ(PIPEBSTAT);
|
|
error->instpm = I915_READ(INSTPM);
|
|
if (INTEL_INFO(dev)->gen < 4) {
|
|
error->ipeir = I915_READ(IPEIR);
|
|
error->ipehr = I915_READ(IPEHR);
|
|
error->instdone = I915_READ(INSTDONE);
|
|
error->acthd = I915_READ(ACTHD);
|
|
error->bbaddr = 0;
|
|
} else {
|
|
error->ipeir = I915_READ(IPEIR_I965);
|
|
error->ipehr = I915_READ(IPEHR_I965);
|
|
error->instdone = I915_READ(INSTDONE_I965);
|
|
error->instps = I915_READ(INSTPS);
|
|
error->instdone1 = I915_READ(INSTDONE1);
|
|
error->acthd = I915_READ(ACTHD_I965);
|
|
error->bbaddr = I915_READ64(BB_ADDR);
|
|
}
|
|
|
|
bbaddr = i915_ringbuffer_last_batch(dev);
|
|
|
|
/* Grab the current batchbuffer, most likely to have crashed. */
|
|
batchbuffer[0] = NULL;
|
|
batchbuffer[1] = NULL;
|
|
count = 0;
|
|
list_for_each_entry(obj_priv,
|
|
&dev_priv->render_ring.active_list, list) {
|
|
|
|
struct drm_gem_object *obj = &obj_priv->base;
|
|
|
|
if (batchbuffer[0] == NULL &&
|
|
bbaddr >= obj_priv->gtt_offset &&
|
|
bbaddr < obj_priv->gtt_offset + obj->size)
|
|
batchbuffer[0] = obj;
|
|
|
|
if (batchbuffer[1] == NULL &&
|
|
error->acthd >= obj_priv->gtt_offset &&
|
|
error->acthd < obj_priv->gtt_offset + obj->size)
|
|
batchbuffer[1] = obj;
|
|
|
|
count++;
|
|
}
|
|
/* Scan the other lists for completeness for those bizarre errors. */
|
|
if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
|
|
list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
|
|
struct drm_gem_object *obj = &obj_priv->base;
|
|
|
|
if (batchbuffer[0] == NULL &&
|
|
bbaddr >= obj_priv->gtt_offset &&
|
|
bbaddr < obj_priv->gtt_offset + obj->size)
|
|
batchbuffer[0] = obj;
|
|
|
|
if (batchbuffer[1] == NULL &&
|
|
error->acthd >= obj_priv->gtt_offset &&
|
|
error->acthd < obj_priv->gtt_offset + obj->size)
|
|
batchbuffer[1] = obj;
|
|
|
|
if (batchbuffer[0] && batchbuffer[1])
|
|
break;
|
|
}
|
|
}
|
|
if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
|
|
list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
|
|
struct drm_gem_object *obj = &obj_priv->base;
|
|
|
|
if (batchbuffer[0] == NULL &&
|
|
bbaddr >= obj_priv->gtt_offset &&
|
|
bbaddr < obj_priv->gtt_offset + obj->size)
|
|
batchbuffer[0] = obj;
|
|
|
|
if (batchbuffer[1] == NULL &&
|
|
error->acthd >= obj_priv->gtt_offset &&
|
|
error->acthd < obj_priv->gtt_offset + obj->size)
|
|
batchbuffer[1] = obj;
|
|
|
|
if (batchbuffer[0] && batchbuffer[1])
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* We need to copy these to an anonymous buffer as the simplest
|
|
* method to avoid being overwritten by userpace.
|
|
*/
|
|
error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
|
|
if (batchbuffer[1] != batchbuffer[0])
|
|
error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
|
|
else
|
|
error->batchbuffer[1] = NULL;
|
|
|
|
/* Record the ringbuffer */
|
|
error->ringbuffer = i915_error_object_create(dev,
|
|
dev_priv->render_ring.gem_object);
|
|
|
|
/* Record buffers on the active list. */
|
|
error->active_bo = NULL;
|
|
error->active_bo_count = 0;
|
|
|
|
if (count)
|
|
error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
|
|
GFP_ATOMIC);
|
|
|
|
if (error->active_bo) {
|
|
int i = 0;
|
|
list_for_each_entry(obj_priv,
|
|
&dev_priv->render_ring.active_list, list) {
|
|
struct drm_gem_object *obj = &obj_priv->base;
|
|
|
|
error->active_bo[i].size = obj->size;
|
|
error->active_bo[i].name = obj->name;
|
|
error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
|
|
error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
|
|
error->active_bo[i].read_domains = obj->read_domains;
|
|
error->active_bo[i].write_domain = obj->write_domain;
|
|
error->active_bo[i].fence_reg = obj_priv->fence_reg;
|
|
error->active_bo[i].pinned = 0;
|
|
if (obj_priv->pin_count > 0)
|
|
error->active_bo[i].pinned = 1;
|
|
if (obj_priv->user_pin_count > 0)
|
|
error->active_bo[i].pinned = -1;
|
|
error->active_bo[i].tiling = obj_priv->tiling_mode;
|
|
error->active_bo[i].dirty = obj_priv->dirty;
|
|
error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
|
|
|
|
if (++i == count)
|
|
break;
|
|
}
|
|
error->active_bo_count = i;
|
|
}
|
|
|
|
do_gettimeofday(&error->time);
|
|
|
|
error->overlay = intel_overlay_capture_error_state(dev);
|
|
|
|
spin_lock_irqsave(&dev_priv->error_lock, flags);
|
|
if (dev_priv->first_error == NULL) {
|
|
dev_priv->first_error = error;
|
|
error = NULL;
|
|
}
|
|
spin_unlock_irqrestore(&dev_priv->error_lock, flags);
|
|
|
|
if (error)
|
|
i915_error_state_free(dev, error);
|
|
}
|
|
|
|
void i915_destroy_error_state(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_i915_error_state *error;
|
|
|
|
spin_lock(&dev_priv->error_lock);
|
|
error = dev_priv->first_error;
|
|
dev_priv->first_error = NULL;
|
|
spin_unlock(&dev_priv->error_lock);
|
|
|
|
if (error)
|
|
i915_error_state_free(dev, error);
|
|
}
|
|
#else
|
|
#define i915_capture_error_state(x)
|
|
#endif
|
|
|
|
static void i915_report_and_clear_eir(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
u32 eir = I915_READ(EIR);
|
|
|
|
if (!eir)
|
|
return;
|
|
|
|
printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
|
|
eir);
|
|
|
|
if (IS_G4X(dev)) {
|
|
if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
|
|
u32 ipeir = I915_READ(IPEIR_I965);
|
|
|
|
printk(KERN_ERR " IPEIR: 0x%08x\n",
|
|
I915_READ(IPEIR_I965));
|
|
printk(KERN_ERR " IPEHR: 0x%08x\n",
|
|
I915_READ(IPEHR_I965));
|
|
printk(KERN_ERR " INSTDONE: 0x%08x\n",
|
|
I915_READ(INSTDONE_I965));
|
|
printk(KERN_ERR " INSTPS: 0x%08x\n",
|
|
I915_READ(INSTPS));
|
|
printk(KERN_ERR " INSTDONE1: 0x%08x\n",
|
|
I915_READ(INSTDONE1));
|
|
printk(KERN_ERR " ACTHD: 0x%08x\n",
|
|
I915_READ(ACTHD_I965));
|
|
I915_WRITE(IPEIR_I965, ipeir);
|
|
(void)I915_READ(IPEIR_I965);
|
|
}
|
|
if (eir & GM45_ERROR_PAGE_TABLE) {
|
|
u32 pgtbl_err = I915_READ(PGTBL_ER);
|
|
printk(KERN_ERR "page table error\n");
|
|
printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
|
|
pgtbl_err);
|
|
I915_WRITE(PGTBL_ER, pgtbl_err);
|
|
(void)I915_READ(PGTBL_ER);
|
|
}
|
|
}
|
|
|
|
if (!IS_GEN2(dev)) {
|
|
if (eir & I915_ERROR_PAGE_TABLE) {
|
|
u32 pgtbl_err = I915_READ(PGTBL_ER);
|
|
printk(KERN_ERR "page table error\n");
|
|
printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
|
|
pgtbl_err);
|
|
I915_WRITE(PGTBL_ER, pgtbl_err);
|
|
(void)I915_READ(PGTBL_ER);
|
|
}
|
|
}
|
|
|
|
if (eir & I915_ERROR_MEMORY_REFRESH) {
|
|
u32 pipea_stats = I915_READ(PIPEASTAT);
|
|
u32 pipeb_stats = I915_READ(PIPEBSTAT);
|
|
|
|
printk(KERN_ERR "memory refresh error\n");
|
|
printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
|
|
pipea_stats);
|
|
printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
|
|
pipeb_stats);
|
|
/* pipestat has already been acked */
|
|
}
|
|
if (eir & I915_ERROR_INSTRUCTION) {
|
|
printk(KERN_ERR "instruction error\n");
|
|
printk(KERN_ERR " INSTPM: 0x%08x\n",
|
|
I915_READ(INSTPM));
|
|
if (INTEL_INFO(dev)->gen < 4) {
|
|
u32 ipeir = I915_READ(IPEIR);
|
|
|
|
printk(KERN_ERR " IPEIR: 0x%08x\n",
|
|
I915_READ(IPEIR));
|
|
printk(KERN_ERR " IPEHR: 0x%08x\n",
|
|
I915_READ(IPEHR));
|
|
printk(KERN_ERR " INSTDONE: 0x%08x\n",
|
|
I915_READ(INSTDONE));
|
|
printk(KERN_ERR " ACTHD: 0x%08x\n",
|
|
I915_READ(ACTHD));
|
|
I915_WRITE(IPEIR, ipeir);
|
|
(void)I915_READ(IPEIR);
|
|
} else {
|
|
u32 ipeir = I915_READ(IPEIR_I965);
|
|
|
|
printk(KERN_ERR " IPEIR: 0x%08x\n",
|
|
I915_READ(IPEIR_I965));
|
|
printk(KERN_ERR " IPEHR: 0x%08x\n",
|
|
I915_READ(IPEHR_I965));
|
|
printk(KERN_ERR " INSTDONE: 0x%08x\n",
|
|
I915_READ(INSTDONE_I965));
|
|
printk(KERN_ERR " INSTPS: 0x%08x\n",
|
|
I915_READ(INSTPS));
|
|
printk(KERN_ERR " INSTDONE1: 0x%08x\n",
|
|
I915_READ(INSTDONE1));
|
|
printk(KERN_ERR " ACTHD: 0x%08x\n",
|
|
I915_READ(ACTHD_I965));
|
|
I915_WRITE(IPEIR_I965, ipeir);
|
|
(void)I915_READ(IPEIR_I965);
|
|
}
|
|
}
|
|
|
|
I915_WRITE(EIR, eir);
|
|
(void)I915_READ(EIR);
|
|
eir = I915_READ(EIR);
|
|
if (eir) {
|
|
/*
|
|
* some errors might have become stuck,
|
|
* mask them.
|
|
*/
|
|
DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
|
|
I915_WRITE(EMR, I915_READ(EMR) | eir);
|
|
I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* i915_handle_error - handle an error interrupt
|
|
* @dev: drm device
|
|
*
|
|
* Do some basic checking of regsiter state at error interrupt time and
|
|
* dump it to the syslog. Also call i915_capture_error_state() to make
|
|
* sure we get a record and make it available in debugfs. Fire a uevent
|
|
* so userspace knows something bad happened (should trigger collection
|
|
* of a ring dump etc.).
|
|
*/
|
|
static void i915_handle_error(struct drm_device *dev, bool wedged)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
i915_capture_error_state(dev);
|
|
i915_report_and_clear_eir(dev);
|
|
|
|
if (wedged) {
|
|
INIT_COMPLETION(dev_priv->error_completion);
|
|
atomic_set(&dev_priv->mm.wedged, 1);
|
|
|
|
/*
|
|
* Wakeup waiting processes so they don't hang
|
|
*/
|
|
wake_up_all(&dev_priv->render_ring.irq_queue);
|
|
if (HAS_BSD(dev))
|
|
wake_up_all(&dev_priv->bsd_ring.irq_queue);
|
|
}
|
|
|
|
queue_work(dev_priv->wq, &dev_priv->error_work);
|
|
}
|
|
|
|
static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
struct drm_i915_gem_object *obj_priv;
|
|
struct intel_unpin_work *work;
|
|
unsigned long flags;
|
|
bool stall_detected;
|
|
|
|
/* Ignore early vblank irqs */
|
|
if (intel_crtc == NULL)
|
|
return;
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
work = intel_crtc->unpin_work;
|
|
|
|
if (work == NULL || work->pending || !work->enable_stall_check) {
|
|
/* Either the pending flip IRQ arrived, or we're too early. Don't check */
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
return;
|
|
}
|
|
|
|
/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
|
|
obj_priv = to_intel_bo(work->pending_flip_obj);
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
|
int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
|
|
stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
|
|
} else {
|
|
int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
|
|
stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
|
|
crtc->y * crtc->fb->pitch +
|
|
crtc->x * crtc->fb->bits_per_pixel/8);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
if (stall_detected) {
|
|
DRM_DEBUG_DRIVER("Pageflip stall detected\n");
|
|
intel_prepare_page_flip(dev, intel_crtc->plane);
|
|
}
|
|
}
|
|
|
|
irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
|
|
{
|
|
struct drm_device *dev = (struct drm_device *) arg;
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
struct drm_i915_master_private *master_priv;
|
|
u32 iir, new_iir;
|
|
u32 pipea_stats, pipeb_stats;
|
|
u32 vblank_status;
|
|
int vblank = 0;
|
|
unsigned long irqflags;
|
|
int irq_received;
|
|
int ret = IRQ_NONE;
|
|
struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
|
|
|
|
atomic_inc(&dev_priv->irq_received);
|
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
return ironlake_irq_handler(dev);
|
|
|
|
iir = I915_READ(IIR);
|
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
|
vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
|
|
else
|
|
vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
|
|
|
|
for (;;) {
|
|
irq_received = iir != 0;
|
|
|
|
/* Can't rely on pipestat interrupt bit in iir as it might
|
|
* have been cleared after the pipestat interrupt was received.
|
|
* It doesn't set the bit in iir again, but it still produces
|
|
* interrupts (for non-MSI).
|
|
*/
|
|
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
|
|
pipea_stats = I915_READ(PIPEASTAT);
|
|
pipeb_stats = I915_READ(PIPEBSTAT);
|
|
|
|
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
|
|
i915_handle_error(dev, false);
|
|
|
|
/*
|
|
* Clear the PIPE(A|B)STAT regs before the IIR
|
|
*/
|
|
if (pipea_stats & 0x8000ffff) {
|
|
if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
|
|
DRM_DEBUG_DRIVER("pipe a underrun\n");
|
|
I915_WRITE(PIPEASTAT, pipea_stats);
|
|
irq_received = 1;
|
|
}
|
|
|
|
if (pipeb_stats & 0x8000ffff) {
|
|
if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
|
|
DRM_DEBUG_DRIVER("pipe b underrun\n");
|
|
I915_WRITE(PIPEBSTAT, pipeb_stats);
|
|
irq_received = 1;
|
|
}
|
|
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
|
|
|
|
if (!irq_received)
|
|
break;
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
/* Consume port. Then clear IIR or we'll miss events */
|
|
if ((I915_HAS_HOTPLUG(dev)) &&
|
|
(iir & I915_DISPLAY_PORT_INTERRUPT)) {
|
|
u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
|
|
|
|
DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
|
|
hotplug_status);
|
|
if (hotplug_status & dev_priv->hotplug_supported_mask)
|
|
queue_work(dev_priv->wq,
|
|
&dev_priv->hotplug_work);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
|
|
I915_READ(PORT_HOTPLUG_STAT);
|
|
}
|
|
|
|
I915_WRITE(IIR, iir);
|
|
new_iir = I915_READ(IIR); /* Flush posted writes */
|
|
|
|
if (dev->primary->master) {
|
|
master_priv = dev->primary->master->driver_priv;
|
|
if (master_priv->sarea_priv)
|
|
master_priv->sarea_priv->last_dispatch =
|
|
READ_BREADCRUMB(dev_priv);
|
|
}
|
|
|
|
if (iir & I915_USER_INTERRUPT) {
|
|
u32 seqno = render_ring->get_seqno(dev, render_ring);
|
|
render_ring->irq_gem_seqno = seqno;
|
|
trace_i915_gem_request_complete(dev, seqno);
|
|
wake_up_all(&dev_priv->render_ring.irq_queue);
|
|
dev_priv->hangcheck_count = 0;
|
|
mod_timer(&dev_priv->hangcheck_timer,
|
|
jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
|
|
}
|
|
|
|
if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
|
|
wake_up_all(&dev_priv->bsd_ring.irq_queue);
|
|
|
|
if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
|
|
intel_prepare_page_flip(dev, 0);
|
|
if (dev_priv->flip_pending_is_done)
|
|
intel_finish_page_flip_plane(dev, 0);
|
|
}
|
|
|
|
if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
|
|
intel_prepare_page_flip(dev, 1);
|
|
if (dev_priv->flip_pending_is_done)
|
|
intel_finish_page_flip_plane(dev, 1);
|
|
}
|
|
|
|
if (pipea_stats & vblank_status) {
|
|
vblank++;
|
|
drm_handle_vblank(dev, 0);
|
|
if (!dev_priv->flip_pending_is_done) {
|
|
i915_pageflip_stall_check(dev, 0);
|
|
intel_finish_page_flip(dev, 0);
|
|
}
|
|
}
|
|
|
|
if (pipeb_stats & vblank_status) {
|
|
vblank++;
|
|
drm_handle_vblank(dev, 1);
|
|
if (!dev_priv->flip_pending_is_done) {
|
|
i915_pageflip_stall_check(dev, 1);
|
|
intel_finish_page_flip(dev, 1);
|
|
}
|
|
}
|
|
|
|
if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
|
|
(pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
|
|
(iir & I915_ASLE_INTERRUPT))
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
/* With MSI, interrupts are only generated when iir
|
|
* transitions from zero to nonzero. If another bit got
|
|
* set while we were handling the existing iir bits, then
|
|
* we would never get another interrupt.
|
|
*
|
|
* This is fine on non-MSI as well, as if we hit this path
|
|
* we avoid exiting the interrupt handler only to generate
|
|
* another one.
|
|
*
|
|
* Note that for MSI this could cause a stray interrupt report
|
|
* if an interrupt landed in the time between writing IIR and
|
|
* the posting read. This should be rare enough to never
|
|
* trigger the 99% of 100,000 interrupts test for disabling
|
|
* stray interrupts.
|
|
*/
|
|
iir = new_iir;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int i915_emit_irq(struct drm_device * dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
|
|
|
i915_kernel_lost_context(dev);
|
|
|
|
DRM_DEBUG_DRIVER("\n");
|
|
|
|
dev_priv->counter++;
|
|
if (dev_priv->counter > 0x7FFFFFFFUL)
|
|
dev_priv->counter = 1;
|
|
if (master_priv->sarea_priv)
|
|
master_priv->sarea_priv->last_enqueue = dev_priv->counter;
|
|
|
|
BEGIN_LP_RING(4);
|
|
OUT_RING(MI_STORE_DWORD_INDEX);
|
|
OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
|
OUT_RING(dev_priv->counter);
|
|
OUT_RING(MI_USER_INTERRUPT);
|
|
ADVANCE_LP_RING();
|
|
|
|
return dev_priv->counter;
|
|
}
|
|
|
|
void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
|
|
|
|
if (dev_priv->trace_irq_seqno == 0)
|
|
render_ring->user_irq_get(dev, render_ring);
|
|
|
|
dev_priv->trace_irq_seqno = seqno;
|
|
}
|
|
|
|
static int i915_wait_irq(struct drm_device * dev, int irq_nr)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
|
int ret = 0;
|
|
struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
|
|
|
|
DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
|
|
READ_BREADCRUMB(dev_priv));
|
|
|
|
if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
|
|
if (master_priv->sarea_priv)
|
|
master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
|
return 0;
|
|
}
|
|
|
|
if (master_priv->sarea_priv)
|
|
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
|
|
|
|
render_ring->user_irq_get(dev, render_ring);
|
|
DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
|
|
READ_BREADCRUMB(dev_priv) >= irq_nr);
|
|
render_ring->user_irq_put(dev, render_ring);
|
|
|
|
if (ret == -EBUSY) {
|
|
DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
|
|
READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Needs the lock as it touches the ring.
|
|
*/
|
|
int i915_irq_emit(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_irq_emit_t *emit = data;
|
|
int result;
|
|
|
|
if (!dev_priv || !dev_priv->render_ring.virtual_start) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
result = i915_emit_irq(dev);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
|
|
DRM_ERROR("copy_to_user\n");
|
|
return -EFAULT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Doesn't need the hardware lock.
|
|
*/
|
|
int i915_irq_wait(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_irq_wait_t *irqwait = data;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return i915_wait_irq(dev, irqwait->irq_seq);
|
|
}
|
|
|
|
/* Called from drm generic code, passed 'crtc' which
|
|
* we use as a pipe index
|
|
*/
|
|
int i915_enable_vblank(struct drm_device *dev, int pipe)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
unsigned long irqflags;
|
|
|
|
if (!i915_pipe_enabled(dev, pipe))
|
|
return -EINVAL;
|
|
|
|
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
|
|
if (HAS_PCH_SPLIT(dev))
|
|
ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
|
|
DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
|
|
else if (INTEL_INFO(dev)->gen >= 4)
|
|
i915_enable_pipestat(dev_priv, pipe,
|
|
PIPE_START_VBLANK_INTERRUPT_ENABLE);
|
|
else
|
|
i915_enable_pipestat(dev_priv, pipe,
|
|
PIPE_VBLANK_INTERRUPT_ENABLE);
|
|
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
|
|
return 0;
|
|
}
|
|
|
|
/* Called from drm generic code, passed 'crtc' which
|
|
* we use as a pipe index
|
|
*/
|
|
void i915_disable_vblank(struct drm_device *dev, int pipe)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
unsigned long irqflags;
|
|
|
|
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
|
|
if (HAS_PCH_SPLIT(dev))
|
|
ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
|
|
DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
|
|
else
|
|
i915_disable_pipestat(dev_priv, pipe,
|
|
PIPE_VBLANK_INTERRUPT_ENABLE |
|
|
PIPE_START_VBLANK_INTERRUPT_ENABLE);
|
|
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
|
|
}
|
|
|
|
void i915_enable_interrupt (struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
if (!HAS_PCH_SPLIT(dev))
|
|
intel_opregion_enable_asle(dev);
|
|
dev_priv->irq_enabled = 1;
|
|
}
|
|
|
|
|
|
/* Set the vblank monitor pipe
|
|
*/
|
|
int i915_vblank_pipe_set(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i915_vblank_pipe_get(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_vblank_pipe_t *pipe = data;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Schedule buffer swap at given vertical blank.
|
|
*/
|
|
int i915_vblank_swap(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
/* The delayed swap mechanism was fundamentally racy, and has been
|
|
* removed. The model was that the client requested a delayed flip/swap
|
|
* from the kernel, then waited for vblank before continuing to perform
|
|
* rendering. The problem was that the kernel might wake the client
|
|
* up before it dispatched the vblank swap (since the lock has to be
|
|
* held while touching the ringbuffer), in which case the client would
|
|
* clear and start the next frame before the swap occurred, and
|
|
* flicker would occur in addition to likely missing the vblank.
|
|
*
|
|
* In the absence of this ioctl, userland falls back to a correct path
|
|
* of waiting for a vblank, then dispatching the swap on its own.
|
|
* Context switching to userland and back is plenty fast enough for
|
|
* meeting the requirements of vblank swapping.
|
|
*/
|
|
return -EINVAL;
|
|
}
|
|
|
|
static struct drm_i915_gem_request *
|
|
i915_get_tail_request(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
return list_entry(dev_priv->render_ring.request_list.prev,
|
|
struct drm_i915_gem_request, list);
|
|
}
|
|
|
|
/**
|
|
* This is called when the chip hasn't reported back with completed
|
|
* batchbuffers in a long time. The first time this is called we simply record
|
|
* ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
|
|
* again, we assume the chip is wedged and try to fix it.
|
|
*/
|
|
void i915_hangcheck_elapsed(unsigned long data)
|
|
{
|
|
struct drm_device *dev = (struct drm_device *)data;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
uint32_t acthd, instdone, instdone1;
|
|
|
|
if (INTEL_INFO(dev)->gen < 4) {
|
|
acthd = I915_READ(ACTHD);
|
|
instdone = I915_READ(INSTDONE);
|
|
instdone1 = 0;
|
|
} else {
|
|
acthd = I915_READ(ACTHD_I965);
|
|
instdone = I915_READ(INSTDONE_I965);
|
|
instdone1 = I915_READ(INSTDONE1);
|
|
}
|
|
|
|
/* If all work is done then ACTHD clearly hasn't advanced. */
|
|
if (list_empty(&dev_priv->render_ring.request_list) ||
|
|
i915_seqno_passed(dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring),
|
|
i915_get_tail_request(dev)->seqno)) {
|
|
bool missed_wakeup = false;
|
|
|
|
dev_priv->hangcheck_count = 0;
|
|
|
|
/* Issue a wake-up to catch stuck h/w. */
|
|
if (dev_priv->render_ring.waiting_gem_seqno &&
|
|
waitqueue_active(&dev_priv->render_ring.irq_queue)) {
|
|
wake_up_all(&dev_priv->render_ring.irq_queue);
|
|
missed_wakeup = true;
|
|
}
|
|
|
|
if (dev_priv->bsd_ring.waiting_gem_seqno &&
|
|
waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
|
|
wake_up_all(&dev_priv->bsd_ring.irq_queue);
|
|
missed_wakeup = true;
|
|
}
|
|
|
|
if (missed_wakeup)
|
|
DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
|
|
return;
|
|
}
|
|
|
|
if (dev_priv->last_acthd == acthd &&
|
|
dev_priv->last_instdone == instdone &&
|
|
dev_priv->last_instdone1 == instdone1) {
|
|
if (dev_priv->hangcheck_count++ > 1) {
|
|
DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
|
|
|
|
if (!IS_GEN2(dev)) {
|
|
/* Is the chip hanging on a WAIT_FOR_EVENT?
|
|
* If so we can simply poke the RB_WAIT bit
|
|
* and break the hang. This should work on
|
|
* all but the second generation chipsets.
|
|
*/
|
|
u32 tmp = I915_READ(PRB0_CTL);
|
|
if (tmp & RING_WAIT) {
|
|
I915_WRITE(PRB0_CTL, tmp);
|
|
POSTING_READ(PRB0_CTL);
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
i915_handle_error(dev, true);
|
|
return;
|
|
}
|
|
} else {
|
|
dev_priv->hangcheck_count = 0;
|
|
|
|
dev_priv->last_acthd = acthd;
|
|
dev_priv->last_instdone = instdone;
|
|
dev_priv->last_instdone1 = instdone1;
|
|
}
|
|
|
|
out:
|
|
/* Reset timer case chip hangs without another request being added */
|
|
mod_timer(&dev_priv->hangcheck_timer,
|
|
jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
|
|
}
|
|
|
|
/* drm_dma.h hooks
|
|
*/
|
|
static void ironlake_irq_preinstall(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
I915_WRITE(HWSTAM, 0xeffe);
|
|
|
|
/* XXX hotplug from PCH */
|
|
|
|
I915_WRITE(DEIMR, 0xffffffff);
|
|
I915_WRITE(DEIER, 0x0);
|
|
(void) I915_READ(DEIER);
|
|
|
|
/* and GT */
|
|
I915_WRITE(GTIMR, 0xffffffff);
|
|
I915_WRITE(GTIER, 0x0);
|
|
(void) I915_READ(GTIER);
|
|
|
|
/* south display irq */
|
|
I915_WRITE(SDEIMR, 0xffffffff);
|
|
I915_WRITE(SDEIER, 0x0);
|
|
(void) I915_READ(SDEIER);
|
|
}
|
|
|
|
static int ironlake_irq_postinstall(struct drm_device *dev)
|
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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/* enable kind of interrupts always enabled */
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u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
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DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
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u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
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u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
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SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
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dev_priv->irq_mask_reg = ~display_mask;
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dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
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/* should always can generate irq */
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I915_WRITE(DEIIR, I915_READ(DEIIR));
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I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
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I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
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(void) I915_READ(DEIER);
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if (IS_GEN6(dev))
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render_mask = GT_PIPE_NOTIFY | GT_GEN6_BSD_USER_INTERRUPT;
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dev_priv->gt_irq_mask_reg = ~render_mask;
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dev_priv->gt_irq_enable_reg = render_mask;
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
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if (IS_GEN6(dev)) {
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I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
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I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
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}
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I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
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(void) I915_READ(GTIER);
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dev_priv->pch_irq_mask_reg = ~hotplug_mask;
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dev_priv->pch_irq_enable_reg = hotplug_mask;
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I915_WRITE(SDEIIR, I915_READ(SDEIIR));
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I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
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I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
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(void) I915_READ(SDEIER);
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if (IS_IRONLAKE_M(dev)) {
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/* Clear & enable PCU event interrupts */
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I915_WRITE(DEIIR, DE_PCU_EVENT);
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I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
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ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
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}
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return 0;
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}
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void i915_driver_irq_preinstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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atomic_set(&dev_priv->irq_received, 0);
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INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
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INIT_WORK(&dev_priv->error_work, i915_error_work_func);
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if (HAS_PCH_SPLIT(dev)) {
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ironlake_irq_preinstall(dev);
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return;
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}
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if (I915_HAS_HOTPLUG(dev)) {
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I915_WRITE(PORT_HOTPLUG_EN, 0);
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I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
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}
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I915_WRITE(HWSTAM, 0xeffe);
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I915_WRITE(PIPEASTAT, 0);
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I915_WRITE(PIPEBSTAT, 0);
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I915_WRITE(IMR, 0xffffffff);
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I915_WRITE(IER, 0x0);
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(void) I915_READ(IER);
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}
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/*
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* Must be called after intel_modeset_init or hotplug interrupts won't be
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* enabled correctly.
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*/
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int i915_driver_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
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u32 error_mask;
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DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
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if (HAS_BSD(dev))
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DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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if (HAS_PCH_SPLIT(dev))
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return ironlake_irq_postinstall(dev);
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/* Unmask the interrupts that we always want on. */
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dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
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dev_priv->pipestat[0] = 0;
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dev_priv->pipestat[1] = 0;
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if (I915_HAS_HOTPLUG(dev)) {
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/* Enable in IER... */
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enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
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/* and unmask in IMR */
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dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
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}
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/*
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* Enable some error detection, note the instruction error mask
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* bit is reserved, so we leave it masked.
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*/
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if (IS_G4X(dev)) {
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error_mask = ~(GM45_ERROR_PAGE_TABLE |
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GM45_ERROR_MEM_PRIV |
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GM45_ERROR_CP_PRIV |
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I915_ERROR_MEMORY_REFRESH);
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} else {
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error_mask = ~(I915_ERROR_PAGE_TABLE |
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I915_ERROR_MEMORY_REFRESH);
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}
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I915_WRITE(EMR, error_mask);
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I915_WRITE(IMR, dev_priv->irq_mask_reg);
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I915_WRITE(IER, enable_mask);
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(void) I915_READ(IER);
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if (I915_HAS_HOTPLUG(dev)) {
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u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
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/* Note HDMI and DP share bits */
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if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
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hotplug_en |= HDMIB_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
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hotplug_en |= HDMIC_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
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hotplug_en |= HDMID_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
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hotplug_en |= SDVOC_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
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hotplug_en |= SDVOB_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
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hotplug_en |= CRT_HOTPLUG_INT_EN;
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/* Programming the CRT detection parameters tends
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to generate a spurious hotplug event about three
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seconds later. So just do it once.
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*/
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if (IS_G4X(dev))
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hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
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hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
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}
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/* Ignore TV since it's buggy */
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I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
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}
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intel_opregion_enable_asle(dev);
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return 0;
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}
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static void ironlake_irq_uninstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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I915_WRITE(HWSTAM, 0xffffffff);
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I915_WRITE(DEIMR, 0xffffffff);
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I915_WRITE(DEIER, 0x0);
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I915_WRITE(DEIIR, I915_READ(DEIIR));
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I915_WRITE(GTIMR, 0xffffffff);
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I915_WRITE(GTIER, 0x0);
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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}
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void i915_driver_irq_uninstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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if (!dev_priv)
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return;
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dev_priv->vblank_pipe = 0;
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if (HAS_PCH_SPLIT(dev)) {
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ironlake_irq_uninstall(dev);
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return;
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}
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if (I915_HAS_HOTPLUG(dev)) {
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I915_WRITE(PORT_HOTPLUG_EN, 0);
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I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
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}
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I915_WRITE(HWSTAM, 0xffffffff);
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I915_WRITE(PIPEASTAT, 0);
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I915_WRITE(PIPEBSTAT, 0);
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I915_WRITE(IMR, 0xffffffff);
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I915_WRITE(IER, 0x0);
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I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
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I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
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I915_WRITE(IIR, I915_READ(IIR));
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}
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