8a44971841
This patch is meant to cleanup the handling of read_barrier_depends and
smp_read_barrier_depends. In multiple spots in the kernel headers
read_barrier_depends is defined as "do {} while (0)", however we then go
into the SMP vs non-SMP sections and have the SMP version reference
read_barrier_depends, and the non-SMP define it as yet another empty
do/while.
With this commit I went through and cleaned out the duplicate definitions
and reduced the number of definitions down to 2 per header. In addition I
moved the 50 line comments for the macro from the x86 and mips headers that
defined it as an empty do/while to those that were actually defining the
macro, alpha and blackfin.
Signed-off-by: Alexander Duyck <alexander.h.duyck@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
91 lines
2.7 KiB
C
91 lines
2.7 KiB
C
/*
|
|
* Memory barrier definitions. This is based on information published
|
|
* in the Processor Abstraction Layer and the System Abstraction Layer
|
|
* manual.
|
|
*
|
|
* Copyright (C) 1998-2003 Hewlett-Packard Co
|
|
* David Mosberger-Tang <davidm@hpl.hp.com>
|
|
* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
|
|
* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
|
|
*/
|
|
#ifndef _ASM_IA64_BARRIER_H
|
|
#define _ASM_IA64_BARRIER_H
|
|
|
|
#include <linux/compiler.h>
|
|
|
|
/*
|
|
* Macros to force memory ordering. In these descriptions, "previous"
|
|
* and "subsequent" refer to program order; "visible" means that all
|
|
* architecturally visible effects of a memory access have occurred
|
|
* (at a minimum, this means the memory has been read or written).
|
|
*
|
|
* wmb(): Guarantees that all preceding stores to memory-
|
|
* like regions are visible before any subsequent
|
|
* stores and that all following stores will be
|
|
* visible only after all previous stores.
|
|
* rmb(): Like wmb(), but for reads.
|
|
* mb(): wmb()/rmb() combo, i.e., all previous memory
|
|
* accesses are visible before all subsequent
|
|
* accesses and vice versa. This is also known as
|
|
* a "fence."
|
|
*
|
|
* Note: "mb()" and its variants cannot be used as a fence to order
|
|
* accesses to memory mapped I/O registers. For that, mf.a needs to
|
|
* be used. However, we don't want to always use mf.a because (a)
|
|
* it's (presumably) much slower than mf and (b) mf.a is supported for
|
|
* sequential memory pages only.
|
|
*/
|
|
#define mb() ia64_mf()
|
|
#define rmb() mb()
|
|
#define wmb() mb()
|
|
|
|
#ifdef CONFIG_SMP
|
|
# define smp_mb() mb()
|
|
#else
|
|
# define smp_mb() barrier()
|
|
#endif
|
|
|
|
#define smp_rmb() smp_mb()
|
|
#define smp_wmb() smp_mb()
|
|
|
|
#define read_barrier_depends() do { } while (0)
|
|
#define smp_read_barrier_depends() do { } while (0)
|
|
|
|
#define smp_mb__before_atomic() barrier()
|
|
#define smp_mb__after_atomic() barrier()
|
|
|
|
/*
|
|
* IA64 GCC turns volatile stores into st.rel and volatile loads into ld.acq no
|
|
* need for asm trickery!
|
|
*/
|
|
|
|
#define smp_store_release(p, v) \
|
|
do { \
|
|
compiletime_assert_atomic_type(*p); \
|
|
barrier(); \
|
|
ACCESS_ONCE(*p) = (v); \
|
|
} while (0)
|
|
|
|
#define smp_load_acquire(p) \
|
|
({ \
|
|
typeof(*p) ___p1 = ACCESS_ONCE(*p); \
|
|
compiletime_assert_atomic_type(*p); \
|
|
barrier(); \
|
|
___p1; \
|
|
})
|
|
|
|
/*
|
|
* XXX check on this ---I suspect what Linus really wants here is
|
|
* acquire vs release semantics but we can't discuss this stuff with
|
|
* Linus just yet. Grrr...
|
|
*/
|
|
#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
|
|
|
|
/*
|
|
* The group barrier in front of the rsm & ssm are necessary to ensure
|
|
* that none of the previous instructions in the same group are
|
|
* affected by the rsm/ssm.
|
|
*/
|
|
|
|
#endif /* _ASM_IA64_BARRIER_H */
|